Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2013 Oskar Andero <oskar.andero@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2014 Rose Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * 	   Allan Bendorff Jensen <abj@rosetechnology.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	   Soren Andersen <san@rosetechnology.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Driver for following ADC chips from Microchip Technology's:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * 10 Bit converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * MCP3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * MCP3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * MCP3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * MCP3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * 12 bit converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * MCP3201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * MCP3202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * MCP3204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * MCP3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * 13 bit converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * MCP3301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * 22 bit converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * MCP3550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * MCP3551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * MCP3553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Datasheet can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * https://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf  mcp3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * https://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf  mcp3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * https://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf  mcp3004/08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf  mcp3201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf  mcp3202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf  mcp3204/08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * https://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf  mcp3301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf  mcp3550/1/3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	mcp3001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	mcp3002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	mcp3004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mcp3008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	mcp3201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	mcp3202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	mcp3204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	mcp3208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mcp3301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mcp3550_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mcp3550_60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mcp3551,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	mcp3553,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct mcp320x_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned int conv_time; /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * struct mcp320x - Microchip SPI ADC instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * @spi: SPI slave (parent of the IIO device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * @msg: SPI message to select a channel and receive a value from the ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @transfer: SPI transfers used by @msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @start_conv_msg: SPI message to start a conversion by briefly asserting CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * @start_conv_transfer: SPI transfer used by @start_conv_msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * @reg: regulator generating Vref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * @lock: protects read sequences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @chip_info: ADC properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @rx_buf: buffer for @transfer[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct mcp320x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct spi_transfer transfer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct spi_message start_conv_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct spi_transfer start_conv_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	const struct mcp320x_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u8 tx_buf ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u8 rx_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int mcp320x_channel_to_tx_data(int device_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			const unsigned int channel, bool differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int start_bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	switch (device_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case mcp3002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case mcp3202:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return ((start_bit << 4) | (!differential << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 							(channel << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	case mcp3004:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case mcp3204:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case mcp3008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case mcp3208:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return ((start_bit << 6) | (!differential << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 							(channel << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				  bool differential, int device_index, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (adc->chip_info->conv_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		ret = spi_sync(adc->spi, &adc->start_conv_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		usleep_range(adc->chip_info->conv_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			     adc->chip_info->conv_time + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	memset(&adc->rx_buf, 0, sizeof(adc->rx_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (adc->chip_info->num_channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 							 differential);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ret = spi_sync(adc->spi, &adc->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	switch (device_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	case mcp3001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		*val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case mcp3002:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	case mcp3004:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	case mcp3008:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		*val = (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case mcp3201:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		*val = (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case mcp3202:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	case mcp3204:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	case mcp3208:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		*val = (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	case mcp3301:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		*val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				    | adc->rx_buf[1], 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	case mcp3550_50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case mcp3550_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	case mcp3551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case mcp3553: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		u32 raw = be32_to_cpup((__be32 *)adc->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (!(adc->spi->mode & SPI_CPOL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		 * If the input is within -vref and vref, bit 21 is the sign.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		 * Up to 12% overrange or underrange are allowed, in which case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		 * bit 23 is the sign and bit 0 to 21 is the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		raw >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (raw & BIT(22) && raw & BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			return -EIO; /* cannot have overrange AND underrange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		else if (raw & BIT(22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			raw &= ~BIT(22); /* overrange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		else if (raw & BIT(23) || raw & BIT(21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			raw |= GENMASK(31, 22); /* underrange or negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		*val = (s32)raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int mcp320x_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			    struct iio_chan_spec const *channel, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			    int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct mcp320x *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int device_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	device_index = spi_get_device_id(adc->spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		ret = mcp320x_adc_conversion(adc, channel->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			channel->differential, device_index, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		ret = regulator_get_voltage(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		/* convert regulator output voltage to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		*val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		*val2 = adc->chip_info->resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		ret = IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MCP320X_VOLTAGE_CHANNEL(num)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.channel = (num),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.address = (num),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.type = IIO_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.indexed = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.channel = (chan1),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.channel2 = (chan2),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.address = (chan1),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.differential = 1,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct iio_chan_spec mcp3201_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct iio_chan_spec mcp3202_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	MCP320X_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	MCP320X_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct iio_chan_spec mcp3204_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	MCP320X_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	MCP320X_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	MCP320X_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	MCP320X_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct iio_chan_spec mcp3208_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	MCP320X_VOLTAGE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	MCP320X_VOLTAGE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	MCP320X_VOLTAGE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	MCP320X_VOLTAGE_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	MCP320X_VOLTAGE_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	MCP320X_VOLTAGE_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	MCP320X_VOLTAGE_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	MCP320X_VOLTAGE_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct iio_info mcp320x_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.read_raw = mcp320x_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	[mcp3001] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.resolution = 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	[mcp3002] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.channels = mcp3202_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.num_channels = ARRAY_SIZE(mcp3202_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.resolution = 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	[mcp3004] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.channels = mcp3204_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.num_channels = ARRAY_SIZE(mcp3204_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.resolution = 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	[mcp3008] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.channels = mcp3208_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.num_channels = ARRAY_SIZE(mcp3208_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.resolution = 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	[mcp3201] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.resolution = 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	[mcp3202] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.channels = mcp3202_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.num_channels = ARRAY_SIZE(mcp3202_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.resolution = 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	[mcp3204] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		.channels = mcp3204_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.num_channels = ARRAY_SIZE(mcp3204_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.resolution = 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	[mcp3208] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.channels = mcp3208_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.num_channels = ARRAY_SIZE(mcp3208_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.resolution = 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	[mcp3301] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.resolution = 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	[mcp3550_50] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.resolution = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		/* 2% max deviation + 144 clock periods to exit shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.conv_time = 80000 * 1.02 + 144000 / 102.4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	[mcp3550_60] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.resolution = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.conv_time = 66670 * 1.02 + 144000 / 122.88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	[mcp3551] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.resolution = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.conv_time = 73100 * 1.02 + 144000 / 112.64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	[mcp3553] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.channels = mcp3201_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.num_channels = ARRAY_SIZE(mcp3201_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.resolution = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.conv_time = 16670 * 1.02 + 144000 / 122.88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int mcp320x_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	struct mcp320x *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	const struct mcp320x_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	int ret, device_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	indio_dev->info = &mcp320x_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	device_index = spi_get_device_id(spi)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	chip_info = &mcp320x_chip_infos[device_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	indio_dev->channels = chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	indio_dev->num_channels = chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	adc->chip_info = chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	adc->transfer[0].tx_buf = &adc->tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	adc->transfer[0].len = sizeof(adc->tx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	adc->transfer[1].rx_buf = adc->rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (chip_info->num_channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		/* single-channel converters are rx only (no MOSI pin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		spi_message_init_with_transfers(&adc->msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 						&adc->transfer[1], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		spi_message_init_with_transfers(&adc->msg, adc->transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 						ARRAY_SIZE(adc->transfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	switch (device_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	case mcp3550_50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	case mcp3550_60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	case mcp3551:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	case mcp3553:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		/* rx len increases from 24 to 25 bit in SPI mode 0,0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		if (!(spi->mode & SPI_CPOL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			adc->transfer[1].len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		/* conversions are started by asserting CS pin for 8 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		adc->start_conv_transfer.delay.value = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		adc->start_conv_transfer.delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		spi_message_init_with_transfers(&adc->start_conv_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 						&adc->start_conv_transfer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		 * If CS was previously kept low (continuous conversion mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		 * and then changed to high, the chip is in shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		 * Sometimes it fails to wake from shutdown and clocks out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		 * only 0xffffff.  The magic sequence of performing two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		 * conversions without delay between them resets the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		 * and ensures all subsequent conversions succeed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	adc->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (IS_ERR(adc->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		return PTR_ERR(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		goto reg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) reg_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int mcp320x_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	struct mcp320x *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct of_device_id mcp320x_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	/* NOTE: The use of compatibles with no vendor prefix is deprecated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	{ .compatible = "mcp3001" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	{ .compatible = "mcp3002" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	{ .compatible = "mcp3004" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	{ .compatible = "mcp3008" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	{ .compatible = "mcp3201" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	{ .compatible = "mcp3202" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	{ .compatible = "mcp3204" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	{ .compatible = "mcp3208" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	{ .compatible = "mcp3301" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	{ .compatible = "microchip,mcp3001" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	{ .compatible = "microchip,mcp3002" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	{ .compatible = "microchip,mcp3004" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	{ .compatible = "microchip,mcp3008" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	{ .compatible = "microchip,mcp3201" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	{ .compatible = "microchip,mcp3202" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	{ .compatible = "microchip,mcp3204" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	{ .compatible = "microchip,mcp3208" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	{ .compatible = "microchip,mcp3301" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	{ .compatible = "microchip,mcp3550-50" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	{ .compatible = "microchip,mcp3550-60" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	{ .compatible = "microchip,mcp3551" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	{ .compatible = "microchip,mcp3553" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct spi_device_id mcp320x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	{ "mcp3001", mcp3001 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	{ "mcp3002", mcp3002 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	{ "mcp3004", mcp3004 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	{ "mcp3008", mcp3008 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	{ "mcp3201", mcp3201 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	{ "mcp3202", mcp3202 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	{ "mcp3204", mcp3204 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	{ "mcp3208", mcp3208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	{ "mcp3301", mcp3301 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	{ "mcp3550-50", mcp3550_50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	{ "mcp3550-60", mcp3550_60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	{ "mcp3551", mcp3551 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	{ "mcp3553", mcp3553 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_DEVICE_TABLE(spi, mcp320x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct spi_driver mcp320x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		.name = "mcp320x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		.of_match_table = mcp320x_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	.probe = mcp320x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	.remove = mcp320x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	.id_table = mcp320x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) module_spi_driver(mcp320x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_LICENSE("GPL v2");