Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MAX1241 low-power, 12-bit serial ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MAX1241_VAL_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MAX1241_SHUTDOWN_DELAY_USEC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) enum max1241_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	max1241,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct max1241 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct gpio_desc *shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	__be16 data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const struct iio_chan_spec max1241_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 				BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int max1241_read(struct max1241 *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct spi_transfer xfers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		 * Begin conversion by bringing /CS low for at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		 * tconv us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			.len = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			.delay.value = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			.delay.unit = SPI_DELAY_UNIT_USECS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		 * Then read two bytes of data in our RX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			.rx_buf = &adc->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return spi_sync_transfer(adc->spi, xfers, ARRAY_SIZE(xfers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int max1241_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int ret, vref_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct max1241 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		if (adc->shutdown) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			gpiod_set_value(adc->shutdown, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			udelay(MAX1241_SHUTDOWN_DELAY_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			ret = max1241_read(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			gpiod_set_value(adc->shutdown, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			ret = max1241_read(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		*val = (be16_to_cpu(adc->data) >> 3) & MAX1241_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		vref_uV = regulator_get_voltage(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		if (vref_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			return vref_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		*val = vref_uV / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		*val2 = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct iio_info max1241_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.read_raw = max1241_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void max1241_disable_vdd_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct max1241 *adc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct device *dev = &adc->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	err = regulator_disable(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		dev_err(dev, "could not disable vdd regulator.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void max1241_disable_vref_action(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct max1241 *adc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct device *dev = &adc->spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	err = regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		dev_err(dev, "could not disable vref regulator.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int max1241_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct max1241 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	adc->vdd = devm_regulator_get(dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (IS_ERR(adc->vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		dev_err(dev, "failed to get vdd regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return PTR_ERR(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ret = regulator_enable(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ret = devm_add_action_or_reset(dev, max1241_disable_vdd_action, adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		dev_err(dev, "could not set up vdd regulator cleanup action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	adc->vref = devm_regulator_get(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (IS_ERR(adc->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(dev, "failed to get vref regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return PTR_ERR(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ret = regulator_enable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = devm_add_action_or_reset(dev, max1241_disable_vref_action, adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dev_err(dev, "could not set up vref regulator cleanup action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	adc->shutdown = devm_gpiod_get_optional(dev, "shutdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 						GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (IS_ERR(adc->shutdown))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return PTR_ERR(adc->shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (adc->shutdown)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		dev_dbg(dev, "shutdown pin passed, low-power mode enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dev_dbg(dev, "no shutdown pin passed, low-power mode disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	indio_dev->info = &max1241_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	indio_dev->channels = max1241_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	indio_dev->num_channels = ARRAY_SIZE(max1241_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct spi_device_id max1241_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ "max1241", max1241 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct of_device_id max1241_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{ .compatible = "maxim,max1241" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DEVICE_TABLE(of, max1241_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct spi_driver max1241_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.name = "max1241",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.of_match_table = max1241_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.probe = max1241_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.id_table = max1241_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) module_spi_driver(max1241_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_AUTHOR("Alexandru Lazar <alazar@startmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DESCRIPTION("MAX1241 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_LICENSE("GPL v2");