Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * MAX1117/MAX1118/MAX1119 8-bit, dual-channel ADCs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2017 Akinobu Mita <akinobu.mita@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX1117-MAX1119.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * SPI interface connections
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * SPI                MAXIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Master  Direction  MAX1117/8/9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * ------  ---------  -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * nCS        -->     CNVST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * SCK        -->     SCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * MISO       <--     DOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * ------  ---------  -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) enum max1118_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	max1117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	max1118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	max1119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct max1118 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/* Ensure natural alignment of buffer elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		u8 channels[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		s64 ts __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	} scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u8 data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX1118_CHANNEL(ch)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.channel = (ch),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.scan_index = ch,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			.realbits = 8,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			.storagebits = 8,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct iio_chan_spec max1118_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MAX1118_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MAX1118_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	IIO_CHAN_SOFT_TIMESTAMP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int max1118_read(struct spi_device *spi, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct max1118 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct spi_transfer xfers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		 * To select CH1 for conversion, CNVST pin must be brought high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		 * and low for a second time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			.len = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			.delay = {	/* > CNVST Low Time 100 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				.value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				.unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			.cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 * The acquisition interval begins with the falling edge of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		 * CNVST.  The total acquisition and conversion process takes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		 * <7.5us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			.len = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			.delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				.value = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				.unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			.rx_buf = &adc->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			.len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		ret = spi_sync_transfer(spi, xfers + 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		ret = spi_sync_transfer(spi, xfers, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return adc->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int max1118_get_vref_mV(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct max1118 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int vref_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	switch (id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	case max1117:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case max1119:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case max1118:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		vref_uV = regulator_get_voltage(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (vref_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			return vref_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return vref_uV / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int max1118_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct max1118 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		*val = max1118_read(adc->spi, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		*val = max1118_get_vref_mV(adc->spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		*val2 = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct iio_info max1118_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.read_raw = max1118_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static irqreturn_t max1118_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct max1118 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int scan_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	for_each_set_bit(scan_index, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		const struct iio_chan_spec *scan_chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				&indio_dev->channels[scan_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		int ret = max1118_read(adc->spi, scan_chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			dev_warn(&adc->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				"failed to get conversion data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		adc->scan.channels[i] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 					   iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int max1118_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct max1118 *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (id->driver_data == max1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		adc->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (IS_ERR(adc->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			dev_err(&spi->dev, "failed to get vref regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			return PTR_ERR(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		ret = regulator_enable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	indio_dev->info = &max1118_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	indio_dev->channels = max1118_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	indio_dev->num_channels = ARRAY_SIZE(max1118_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * To reinitiate a conversion on CH0, it is necessary to allow for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * conversion to be complete and all of the data to be read out.  Once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * a conversion has been completed, the MAX1117/MAX1118/MAX1119 will go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * into AutoShutdown mode until the next conversion is initiated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	max1118_read(spi, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					max1118_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		goto err_reg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		goto err_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) err_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err_reg_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (id->driver_data == max1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int max1118_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct max1118 *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (id->driver_data == max1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return regulator_disable(adc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct spi_device_id max1118_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{ "max1117", max1117 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{ "max1118", max1118 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	{ "max1119", max1119 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_DEVICE_TABLE(spi, max1118_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct of_device_id max1118_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ .compatible = "maxim,max1117" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ .compatible = "maxim,max1118" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ .compatible = "maxim,max1119" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DEVICE_TABLE(of, max1118_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct spi_driver max1118_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.name = "max1118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.of_match_table = max1118_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.probe = max1118_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.remove = max1118_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.id_table = max1118_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) module_spi_driver(max1118_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_DESCRIPTION("MAXIM MAX1117/MAX1118/MAX1119 ADCs driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_LICENSE("GPL v2");