^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * iio/adc/max1027.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Philippe Reynes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on linux/drivers/iio/ad7923.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2012 CS Systemes d'Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * max1027.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Partial support for max1027 and similar chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX1027_CONV_REG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAX1027_SETUP_REG BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX1027_AVG_REG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX1027_RST_REG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* conversion register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX1027_TEMP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX1027_SCAN_0_N (0x00 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX1027_SCAN_N_M (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX1027_SCAN_N (0x02 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX1027_NOSCAN (0x03 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX1027_CHAN(n) ((n) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* setup register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX1027_UNIPOLAR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX1027_BIPOLAR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX1027_REF_MODE0 (0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX1027_REF_MODE1 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MAX1027_REF_MODE2 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MAX1027_REF_MODE3 (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX1027_CKS_MODE0 (0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX1027_CKS_MODE1 (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX1027_CKS_MODE2 (0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MAX1027_CKS_MODE3 (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* averaging register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MAX1027_NSCAN_4 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX1027_NSCAN_8 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MAX1027_NSCAN_12 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MAX1027_NSCAN_16 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAX1027_NAVG_4 (0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAX1027_NAVG_8 (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAX1027_NAVG_16 (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAX1027_NAVG_32 (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX1027_AVG_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum max1027_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) max1027,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) max1029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) max1031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) max1227,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) max1229,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) max1231,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct spi_device_id max1027_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {"max1027", max1027},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {"max1029", max1029},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {"max1031", max1031},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {"max1227", max1227},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {"max1229", max1229},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {"max1231", max1231},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_DEVICE_TABLE(spi, max1027_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct of_device_id max1027_adc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .compatible = "maxim,max1027" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { .compatible = "maxim,max1029" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .compatible = "maxim,max1031" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .compatible = "maxim,max1227" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .compatible = "maxim,max1229" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .compatible = "maxim,max1231" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MAX1027_V_CHAN(index, depth) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .channel = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .scan_index = index + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .realbits = depth, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .shift = (depth == 10) ? 2 : 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAX1027_T_CHAN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .type = IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .channel = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .scan_index = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MAX1X27_CHANNELS(depth) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MAX1027_T_CHAN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MAX1027_V_CHAN(0, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MAX1027_V_CHAN(1, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MAX1027_V_CHAN(2, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MAX1027_V_CHAN(3, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MAX1027_V_CHAN(4, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MAX1027_V_CHAN(5, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MAX1027_V_CHAN(6, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MAX1027_V_CHAN(7, depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MAX1X29_CHANNELS(depth) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MAX1X27_CHANNELS(depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MAX1027_V_CHAN(8, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MAX1027_V_CHAN(9, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MAX1027_V_CHAN(10, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MAX1027_V_CHAN(11, depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MAX1X31_CHANNELS(depth) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MAX1X29_CHANNELS(depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MAX1027_V_CHAN(12, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MAX1027_V_CHAN(13, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MAX1027_V_CHAN(14, depth), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MAX1027_V_CHAN(15, depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct iio_chan_spec max1027_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MAX1X27_CHANNELS(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct iio_chan_spec max1029_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MAX1X29_CHANNELS(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct iio_chan_spec max1031_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MAX1X31_CHANNELS(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct iio_chan_spec max1227_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MAX1X27_CHANNELS(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct iio_chan_spec max1229_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MAX1X29_CHANNELS(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct iio_chan_spec max1231_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MAX1X31_CHANNELS(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned long max1027_available_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0x000001ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned long max1029_available_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x00001fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned long max1031_available_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x0001ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct max1027_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const unsigned long *available_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct max1027_chip_info max1027_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [max1027] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .channels = max1027_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .num_channels = ARRAY_SIZE(max1027_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .available_scan_masks = max1027_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [max1029] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .channels = max1029_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .num_channels = ARRAY_SIZE(max1029_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .available_scan_masks = max1029_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [max1031] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .channels = max1031_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .num_channels = ARRAY_SIZE(max1031_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .available_scan_masks = max1031_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [max1227] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .channels = max1227_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_channels = ARRAY_SIZE(max1227_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .available_scan_masks = max1027_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [max1229] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .channels = max1229_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .num_channels = ARRAY_SIZE(max1229_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .available_scan_masks = max1029_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [max1231] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .channels = max1231_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .num_channels = ARRAY_SIZE(max1231_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .available_scan_masks = max1031_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct max1027_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) const struct max1027_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __be16 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 reg ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int max1027_read_single_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct max1027_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (iio_buffer_enabled(indio_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_warn(&indio_dev->dev, "trigger mode already enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Start acquisition on conversion register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "Failed to configure setup register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Configure conversion register with the requested chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MAX1027_NOSCAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (chan->type == IIO_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) st->reg |= MAX1027_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "Failed to configure conversion register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * For an unknown reason, when we use the mode "10" (write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * conversion register), the interrupt doesn't occur every time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * So we just wait 1 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Read result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *val = be16_to_cpu(st->buffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int max1027_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct max1027_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = max1027_read_single_value(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *val2 = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *val = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned reg, unsigned writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct max1027_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 *val = (u8 *)st->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (readval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret = spi_read(st->spi, val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *readval = be16_to_cpu(st->buffer[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *val = (u8)writeval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return spi_write(st->spi, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int max1027_validate_trigger(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct max1027_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (st->trig != trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct max1027_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Start acquisition on cnvst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MAX1027_REF_MODE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Scan from 0 to max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MAX1027_SCAN_N_M | MAX1027_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Start acquisition on conversion register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MAX1027_REF_MODE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static irqreturn_t max1027_trigger_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct iio_poll_func *pf = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct max1027_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* fill buffer with all channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) iio_push_to_buffers(indio_dev, st->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct iio_trigger_ops max1027_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .validate_device = &iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .set_trigger_state = &max1027_set_trigger_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct iio_info max1027_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .read_raw = &max1027_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .validate_trigger = &max1027_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .debugfs_reg_access = &max1027_debugfs_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int max1027_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct max1027_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (indio_dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_err("Can't allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) indio_dev->info = &max1027_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) indio_dev->channels = st->info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) indio_dev->num_channels = st->info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) indio_dev->available_scan_masks = st->info->available_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) st->buffer = devm_kmalloc_array(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) indio_dev->num_channels, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (st->buffer == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(&indio_dev->dev, "Can't allocate buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &max1027_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&indio_dev->dev, "Failed to setup buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) indio_dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (st->trig == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "Failed to allocate iio trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) st->trig->ops = &max1027_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) st->trig->dev.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iio_trigger_set_drvdata(st->trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = devm_iio_trigger_register(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "Failed to register iio trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = devm_request_threaded_irq(&spi->dev, spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iio_trigger_generic_data_rdy_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spi->dev.driver->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Internal reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) st->reg = MAX1027_RST_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Disable averaging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) st->reg = MAX1027_AVG_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = spi_write(st->spi, &st->reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct spi_driver max1027_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "max1027",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .of_match_table = max1027_adc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .probe = max1027_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .id_table = max1027_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) module_spi_driver(max1027_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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