^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * lpc32xx_adc.c - Support for ADC in LPC32XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 3-channel, 10-bit ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * LPC32XX registers definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPC32XXAD_SELECT(x) ((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC32XXAD_CTRL(x) ((x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC32XXAD_VALUE(x) ((x) + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Bit definitions for LPC32XXAD_SELECT: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* constant, always write this value! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC32XXAD_REFm 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* constant, always write this value! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC32XXAD_REFp 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* multiple of this is the channel number: 0, 1, 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC32XXAD_IN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* constant, always write this value! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC32XXAD_INTERNAL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Bit definitions for LPC32XXAD_CTRL: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC32XXAD_STROBE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC32XXAD_PDN_CTRL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Bit definitions for LPC32XXAD_VALUE: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC32XXAD_VALUE_MASK 0x000003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC32XXAD_NAME "lpc32xx-adc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct lpc32xx_adc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *adc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int lpc32xx_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct lpc32xx_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = clk_prepare_enable(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Measurement setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) LPC32XXAD_REFp | LPC32XXAD_REFm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) LPC32XXAD_SELECT(st->adc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Trigger conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) LPC32XXAD_CTRL(st->adc_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) wait_for_completion(&st->completion); /* set by ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_disable_unprepare(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *val = st->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *val = regulator_get_voltage(st->vref) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *val2 = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct iio_info lpc32xx_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .read_raw = &lpc32xx_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LPC32XX_ADC_CHANNEL_BASE(_index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .channel = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .address = LPC32XXAD_IN * _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .scan_index = _index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LPC32XX_ADC_CHANNEL(_index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LPC32XX_ADC_CHANNEL_BASE(_index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LPC32XX_ADC_SCALE_CHANNEL(_index) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LPC32XX_ADC_CHANNEL_BASE(_index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) LPC32XX_ADC_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LPC32XX_ADC_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) LPC32XX_ADC_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) LPC32XX_ADC_SCALE_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) LPC32XX_ADC_SCALE_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) LPC32XX_ADC_SCALE_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct lpc32xx_adc_state *st = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Read value and clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) LPC32XXAD_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) complete(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int lpc32xx_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct lpc32xx_adc_state *st = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct iio_dev *iodev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(&pdev->dev, "failed to get platform I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!iodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) st = iio_priv(iodev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) st->adc_base = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!st->adc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&pdev->dev, "failed mapping memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) st->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (IS_ERR(st->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(&pdev->dev, "failed getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return PTR_ERR(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) LPC32XXAD_NAME, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(&pdev->dev, "failed requesting interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) st->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (IS_ERR(st->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) iodev->channels = lpc32xx_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "Missing vref regulator: No scaling available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) iodev->channels = lpc32xx_adc_iio_scale_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) platform_set_drvdata(pdev, iodev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) init_completion(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) iodev->name = LPC32XXAD_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) iodev->info = &lpc32xx_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) iodev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) retval = devm_iio_device_register(&pdev->dev, iodev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct of_device_id lpc32xx_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .compatible = "nxp,lpc3220-adc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct platform_driver lpc32xx_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .probe = lpc32xx_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = LPC32XXAD_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .of_match_table = lpc32xx_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) module_platform_driver(lpc32xx_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_DESCRIPTION("LPC32XX ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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