^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IIO ADC driver for NXP LPC18xx ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * UNSUPPORTED hardware features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - Hardware triggers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - Burst mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* LPC18XX ADC registers and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC18XX_ADC_CR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC18XX_ADC_CR_CLKDIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC18XX_ADC_CR_PDN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC18XX_ADC_CR_START_NOW (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC18XX_ADC_GDR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Data register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC18XX_ADC_SAMPLE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC18XX_ADC_SAMPLE_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC18XX_ADC_CONV_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Clock should be 4.5 MHz or less */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC18XX_ADC_CLK_TARGET 4500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct lpc18xx_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 cr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LPC18XX_ADC_CHAN(_idx) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .channel = _idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct iio_chan_spec lpc18xx_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) LPC18XX_ADC_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) LPC18XX_ADC_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) LPC18XX_ADC_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) LPC18XX_ADC_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) LPC18XX_ADC_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) LPC18XX_ADC_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) LPC18XX_ADC_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LPC18XX_ADC_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int lpc18xx_adc_read_chan(struct lpc18xx_adc *adc, unsigned int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel(reg, adc->base + LPC18XX_ADC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg & LPC18XX_ADC_CONV_DONE, 3, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_warn(adc->dev, "adc read timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return (reg >> LPC18XX_ADC_SAMPLE_SHIFT) & LPC18XX_ADC_SAMPLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int lpc18xx_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct lpc18xx_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *val = lpc18xx_adc_read_chan(adc, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *val = regulator_get_voltage(adc->vref) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *val2 = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct iio_info lpc18xx_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .read_raw = lpc18xx_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int lpc18xx_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct lpc18xx_adc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) adc->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) adc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (IS_ERR(adc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return PTR_ERR(adc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) adc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (IS_ERR(adc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(&pdev->dev, "error getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return PTR_ERR(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rate = clk_get_rate(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) adc->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(adc->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(&pdev->dev, "error getting regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return PTR_ERR(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) indio_dev->info = &lpc18xx_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) indio_dev->channels = lpc18xx_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) indio_dev->num_channels = ARRAY_SIZE(lpc18xx_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = regulator_enable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(&pdev->dev, "unable to enable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = clk_prepare_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(&pdev->dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto dis_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) LPC18XX_ADC_CR_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(adc->cr_reg, adc->base + LPC18XX_ADC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(&pdev->dev, "unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dis_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(0, adc->base + LPC18XX_ADC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk_disable_unprepare(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dis_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int lpc18xx_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct lpc18xx_adc *adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(0, adc->base + LPC18XX_ADC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk_disable_unprepare(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) regulator_disable(adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct of_device_id lpc18xx_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .compatible = "nxp,lpc1850-adc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_DEVICE_TABLE(of, lpc18xx_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static struct platform_driver lpc18xx_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .probe = lpc18xx_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .remove = lpc18xx_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "lpc18xx-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .of_match_table = lpc18xx_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) module_platform_driver(lpc18xx_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_DESCRIPTION("LPC18xx ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags
| Donate