^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ADC driver for the Ingenic JZ47xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on drivers/mfd/jz4740-adc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/iio/adc/ingenic,adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define JZ_ADC_REG_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define JZ_ADC_REG_CFG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define JZ_ADC_REG_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JZ_ADC_REG_STATUS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define JZ_ADC_REG_ADSAME 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ_ADC_REG_ADWAIT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ_ADC_REG_ADTCH 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ_ADC_REG_ADBDAT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ_ADC_REG_ADSDAT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ_ADC_REG_ADCMD 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ_ADC_REG_ADCLK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ_ADC_REG_ENABLE_PD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JZ_ADC_REG_CFG_BAT_MD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JZ_ADC_REG_ADCMD_YNADC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JZ_ADC_REG_ADCMD_YPADC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define JZ_ADC_REG_ADCMD_XNADC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JZ_ADC_REG_ADCMD_XPADC BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JZ_ADC_REG_ADCMD_VREFPYP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JZ_ADC_REG_ADCMD_VREFPXN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define JZ_ADC_REG_ADCMD_VREFNYN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JZ_ADC_REG_ADCMD_VREFNXP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JZ_ADC_REG_ADCMD_VREFNXN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define JZ_ADC_REG_ADCMD_VREFAUX BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define JZ_ADC_REG_ADCMD_YNGRU BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define JZ_ADC_REG_ADCMD_XNGRU BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define JZ_ADC_REG_ADCMD_XPGRU BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define JZ_ADC_REG_ADCMD_YPSUP BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define JZ_ADC_REG_ADCMD_XNSUP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define JZ_ADC_REG_ADCMD_XPSUP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define JZ_ADC_AUX_VREF 3300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define JZ_ADC_AUX_VREF_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JZ_ADC_BATTERY_LOW_VREF 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define JZ_ADC_BATTERY_LOW_VREF_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define JZ4725B_ADC_BATTERY_HIGH_VREF 7500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define JZ4770_ADC_BATTERY_VREF 1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define JZ4770_ADC_BATTERY_VREF_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define JZ_ADC_IRQ_AUX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define JZ_ADC_IRQ_BATTERY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define JZ_ADC_IRQ_TOUCH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define JZ_ADC_IRQ_PEN_DOWN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define JZ_ADC_IRQ_PEN_UP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define JZ_ADC_IRQ_SLEEP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ingenic_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct ingenic_adc_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int battery_high_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int battery_high_vref_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const int *battery_raw_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) size_t battery_raw_avail_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const int *battery_scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) size_t battery_scale_avail_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int battery_vref_mode: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int has_aux2: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ingenic_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mutex aux_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct ingenic_adc_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool low_vref_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Init ADCMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) readl(adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (mask & 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(JZ_ADC_REG_ADCMD_XNGRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | JZ_ADC_REG_ADCMD_YPADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(JZ_ADC_REG_ADCMD_YNGRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) | JZ_ADC_REG_ADCMD_XPADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (mask & 0xc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(JZ_ADC_REG_ADCMD_XNGRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | JZ_ADC_REG_ADCMD_YNADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(JZ_ADC_REG_ADCMD_YNGRU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) | JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) | JZ_ADC_REG_ADCMD_XNADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (mask & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) | JZ_ADC_REG_ADCMD_YPADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) | JZ_ADC_REG_ADCMD_XPADC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* We're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(0, adc->base + JZ_ADC_REG_ADCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void ingenic_adc_set_config(struct ingenic_adc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint32_t mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint32_t cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cfg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(cfg, adc->base + JZ_ADC_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void ingenic_adc_enable_unlocked(struct ingenic_adc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val = readb(adc->base + JZ_ADC_REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val |= BIT(engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val &= ~BIT(engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writeb(val, adc->base + JZ_ADC_REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void ingenic_adc_enable(struct ingenic_adc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ingenic_adc_enable_unlocked(adc, engine, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int ingenic_adc_capture(struct ingenic_adc *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Disable CMD_SEL temporarily, because it causes wrong VBAT readings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * probably due to the switch of VREF. We must keep the lock here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * avoid races with the buffer enable/disable functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mutex_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cfg = readl(adc->base + JZ_ADC_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(cfg & ~JZ_ADC_REG_CFG_CMD_SEL, adc->base + JZ_ADC_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ingenic_adc_enable_unlocked(adc, engine, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) !(val & BIT(engine)), 250, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ingenic_adc_enable_unlocked(adc, engine, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel(cfg, adc->base + JZ_ADC_REG_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mutex_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct device *dev = iio_dev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) switch (chan->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case INGENIC_ADC_BATTERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!adc->soc_data->battery_vref_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = clk_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dev_err(dev, "Failed to enable clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (val > JZ_ADC_BATTERY_LOW_VREF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ingenic_adc_set_config(adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) JZ_ADC_REG_CFG_BAT_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) adc->low_vref_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ingenic_adc_set_config(adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) JZ_ADC_REG_CFG_BAT_MD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) JZ_ADC_REG_CFG_BAT_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) adc->low_vref_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) clk_disable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const int jz4725b_adc_battery_raw_avail[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const int jz4725b_adc_battery_scale_avail[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const int jz4740_adc_battery_raw_avail[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const int jz4740_adc_battery_scale_avail[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const int jz4770_adc_battery_raw_avail[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const int jz4770_adc_battery_scale_avail[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct clk *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned long parent_rate, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int div_main, div_10us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) parent_clk = clk_get_parent(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!parent_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(dev, "ADC clock has no parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) parent_rate = clk_get_rate(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * The JZ4725B ADC works at 500 kHz to 8 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * We pick the highest rate possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) div_main = DIV_ROUND_UP(parent_rate, 8000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) div_main = clamp(div_main, 1u, 64u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) rate = parent_rate / div_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (rate < 500000 || rate > 8000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(dev, "No valid divider for ADC main clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* We also need a divider that produces a 10us clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) div_10us = DIV_ROUND_UP(rate, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) adc->base + JZ_ADC_REG_ADCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct clk *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long parent_rate, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned int div_main, div_ms, div_10us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) parent_clk = clk_get_parent(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!parent_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(dev, "ADC clock has no parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) parent_rate = clk_get_rate(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * The JZ4770 ADC works at 20 kHz to 200 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * We pick the highest rate possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) div_main = DIV_ROUND_UP(parent_rate, 200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) div_main = clamp(div_main, 1u, 256u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rate = parent_rate / div_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rate < 20000 || rate > 200000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(dev, "No valid divider for ADC main clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* We also need a divider that produces a 10us clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) div_10us = DIV_ROUND_UP(rate, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* And another, which produces a 1ms clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) div_ms = DIV_ROUND_UP(rate, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) adc->base + JZ_ADC_REG_ADCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct iio_chan_spec jz4740_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .extend_name = "aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .channel = INGENIC_ADC_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .extend_name = "battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .channel = INGENIC_ADC_BATTERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct iio_chan_spec jz4770_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .channel = INGENIC_ADC_TOUCH_XP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .scan_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .channel = INGENIC_ADC_TOUCH_YP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .scan_index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .channel = INGENIC_ADC_TOUCH_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .scan_index = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .channel = INGENIC_ADC_TOUCH_YN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .scan_index = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .channel = INGENIC_ADC_TOUCH_XD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .scan_index = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .channel = INGENIC_ADC_TOUCH_YD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .scan_index = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .realbits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .storagebits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .extend_name = "aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .channel = INGENIC_ADC_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .extend_name = "battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .channel = INGENIC_ADC_BATTERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .extend_name = "aux2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .channel = INGENIC_ADC_AUX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .battery_raw_avail = jz4725b_adc_battery_raw_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .battery_scale_avail = jz4725b_adc_battery_scale_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .battery_vref_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .has_aux2 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .channels = jz4740_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .num_channels = ARRAY_SIZE(jz4740_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .init_clk_div = jz4725b_adc_init_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .battery_raw_avail = jz4740_adc_battery_raw_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .battery_scale_avail = jz4740_adc_battery_scale_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .battery_vref_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .has_aux2 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .channels = jz4740_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .num_channels = ARRAY_SIZE(jz4740_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .init_clk_div = NULL, /* no ADCLK register on JZ4740 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .battery_high_vref = JZ4770_ADC_BATTERY_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .battery_raw_avail = jz4770_adc_battery_raw_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .battery_scale_avail = jz4770_adc_battery_scale_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .battery_vref_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .has_aux2 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .channels = jz4770_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .num_channels = ARRAY_SIZE(jz4770_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .init_clk_div = jz4770_adc_init_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) const int **vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int *type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *type = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *length = adc->soc_data->battery_raw_avail_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) *vals = adc->soc_data->battery_raw_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return IIO_AVAIL_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) *type = IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *length = adc->soc_data->battery_scale_avail_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *vals = adc->soc_data->battery_scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int ingenic_adc_read_chan_info_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = clk_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* We cannot sample AUX/AUX2 in parallel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mutex_lock(&adc->aux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (adc->soc_data->has_aux2 && engine == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bit = BIT(chan->channel == INGENIC_ADC_AUX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = ingenic_adc_capture(adc, engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) switch (chan->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case INGENIC_ADC_AUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case INGENIC_ADC_AUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *val = readw(adc->base + JZ_ADC_REG_ADSDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case INGENIC_ADC_BATTERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *val = readw(adc->base + JZ_ADC_REG_ADBDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mutex_unlock(&adc->aux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) clk_disable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ingenic_adc_read_chan_info_raw(iio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) switch (chan->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case INGENIC_ADC_AUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case INGENIC_ADC_AUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *val = JZ_ADC_AUX_VREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) *val2 = JZ_ADC_AUX_VREF_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case INGENIC_ADC_BATTERY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (adc->low_vref_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *val = JZ_ADC_BATTERY_LOW_VREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) *val = adc->soc_data->battery_high_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *val2 = adc->soc_data->battery_high_vref_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int ingenic_adc_of_xlate(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) const struct of_phandle_args *iiospec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!iiospec->args_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) for (i = 0; i < iio_dev->num_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (iio_dev->channels[i].channel == iiospec->args[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void ingenic_adc_clk_cleanup(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) clk_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct iio_info ingenic_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .write_raw = ingenic_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .read_raw = ingenic_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .read_avail = ingenic_adc_read_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .of_xlate = ingenic_adc_of_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = clk_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* It takes significant time for the touchscreen hw to stabilize. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) JZ_ADC_REG_CFG_PULL_UP(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) writew(80, adc->base + JZ_ADC_REG_ADWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) writew(2, adc->base + JZ_ADC_REG_ADSAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writel(0, adc->base + JZ_ADC_REG_ADTCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) JZ_ADC_REG_CFG_CMD_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ingenic_adc_enable(adc, 2, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ingenic_adc_enable(adc, 2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) writew(0, adc->base + JZ_ADC_REG_ADSAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writew(0, adc->base + JZ_ADC_REG_ADWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) clk_disable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .postenable = &ingenic_adc_buffer_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .predisable = &ingenic_adc_buffer_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static irqreturn_t ingenic_adc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct iio_dev *iio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct ingenic_adc *adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned long mask = iio_dev->active_scan_mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 tdat[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (mask & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) tdat[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) iio_push_to_buffers(iio_dev, tdat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int ingenic_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct iio_dev *iio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct ingenic_adc *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) const struct ingenic_adc_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) soc_data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!soc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) adc = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mutex_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mutex_init(&adc->aux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) adc->soc_data = soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_name(dev), iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_err(dev, "Failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) adc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (IS_ERR(adc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return PTR_ERR(adc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) adc->clk = devm_clk_get(dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (IS_ERR(adc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(dev, "Unable to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return PTR_ERR(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = clk_prepare_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Set clock dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (soc_data->init_clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = soc_data->init_clk_div(dev, adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) clk_disable_unprepare(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Put hardware in a known passive state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) usleep_range(2000, 3000); /* Must wait at least 2ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) clk_disable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(dev, "Unable to add action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) iio_dev->name = "jz-adc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) iio_dev->setup_ops = &ingenic_buffer_setup_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) iio_dev->channels = soc_data->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) iio_dev->num_channels = soc_data->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) iio_dev->info = &ingenic_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = devm_iio_device_register(dev, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(dev, "Unable to register IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const struct of_device_id ingenic_adc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) { .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) { .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) { .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static struct platform_driver ingenic_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "ingenic-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .of_match_table = ingenic_adc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .probe = ingenic_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) module_platform_driver(ingenic_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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