^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale i.MX7D ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* ADC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX7D_REG_ADC_CH_A_CFG1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX7D_REG_ADC_CH_A_CFG2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX7D_REG_ADC_CH_B_CFG1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX7D_REG_ADC_CH_B_CFG2 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX7D_REG_ADC_CH_C_CFG1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX7D_REG_ADC_CH_C_CFG2 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX7D_REG_ADC_CH_D_CFG1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX7D_REG_ADC_CH_D_CFG2 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX7D_REG_ADC_CH_SW_CFG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX7D_REG_ADC_TIMER_UNIT 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX7D_REG_ADC_DMA_FIFO 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX7D_REG_ADC_FIFO_STATUS 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX7D_REG_ADC_INT_SIG_EN 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX7D_REG_ADC_INT_EN 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX7D_REG_ADC_INT_STATUS 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX7D_REG_ADC_CHA_B_CNV_RSLT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX7D_REG_ADC_CHC_D_CNV_RSLT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX7D_REG_ADC_CH_SW_CNV_RSLT 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX7D_REG_ADC_DMA_FIFO_DAT 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX7D_REG_ADC_ADC_CFG 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX7D_REG_ADC_CHANNEL_CFG2_BASE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX7D_EACH_CHANNEL_REG_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN (0x1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4 (0x0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8 (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16 (0x2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32 (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64 (0x4 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128 (0x5 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX7D_REG_ADC_ADC_CFG_ADC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX7D_REG_ADC_INT_CHA_COV_INT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX7D_REG_ADC_INT_CHB_COV_INT_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX7D_REG_ADC_INT_CHC_COV_INT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX7D_REG_ADC_INT_CHD_COV_INT_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX7D_REG_ADC_INT_CHANNEL_INT_EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (IMX7D_REG_ADC_INT_CHA_COV_INT_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IMX7D_REG_ADC_INT_CHB_COV_INT_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IMX7D_REG_ADC_INT_CHC_COV_INT_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IMX7D_REG_ADC_INT_CHD_COV_INT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX7D_ADC_TIMEOUT msecs_to_jiffies(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX7D_ADC_INPUT_CLK 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum imx7d_adc_clk_pre_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) IMX7D_ADC_ANALOG_CLK_PRE_DIV_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) IMX7D_ADC_ANALOG_CLK_PRE_DIV_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) IMX7D_ADC_ANALOG_CLK_PRE_DIV_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) IMX7D_ADC_ANALOG_CLK_PRE_DIV_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) IMX7D_ADC_ANALOG_CLK_PRE_DIV_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) IMX7D_ADC_ANALOG_CLK_PRE_DIV_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum imx7d_adc_average_num {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) IMX7D_ADC_AVERAGE_NUM_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) IMX7D_ADC_AVERAGE_NUM_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) IMX7D_ADC_AVERAGE_NUM_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) IMX7D_ADC_AVERAGE_NUM_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct imx7d_adc_feature {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum imx7d_adc_clk_pre_div clk_pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum imx7d_adc_average_num avg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 core_time_unit; /* impact the sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct imx7d_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 pre_div_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct imx7d_adc_feature adc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct imx7d_adc_analogue_core_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 reg_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX7D_ADC_ANALOGUE_CLK_CONFIG(_pre_div, _reg_conf) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .pre_div = (_pre_div), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .reg_config = (_reg_conf), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct imx7d_adc_analogue_core_clk imx7d_adc_analogue_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) IMX7D_ADC_ANALOGUE_CLK_CONFIG(4, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) IMX7D_ADC_ANALOGUE_CLK_CONFIG(8, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) IMX7D_ADC_ANALOGUE_CLK_CONFIG(16, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) IMX7D_ADC_ANALOGUE_CLK_CONFIG(32, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IMX7D_ADC_ANALOGUE_CLK_CONFIG(64, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IMX7D_ADC_ANALOGUE_CLK_CONFIG(128, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX7D_ADC_CHAN(_idx) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .channel = (_idx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct iio_chan_spec imx7d_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IMX7D_ADC_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) IMX7D_ADC_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) IMX7D_ADC_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IMX7D_ADC_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) IMX7D_ADC_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) IMX7D_ADC_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) IMX7D_ADC_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IMX7D_ADC_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) IMX7D_ADC_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) IMX7D_ADC_CHAN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IMX7D_ADC_CHAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) IMX7D_ADC_CHAN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) IMX7D_ADC_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) IMX7D_ADC_CHAN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) IMX7D_ADC_CHAN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) IMX7D_ADC_CHAN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const u32 imx7d_adc_average_num[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void imx7d_adc_feature_config(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) info->adc_feature.core_time_unit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void imx7d_adc_sample_rate_set(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct imx7d_adc_feature *adc_feature = &info->adc_feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct imx7d_adc_analogue_core_clk adc_analogure_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 tmp_cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 sample_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Before sample set, disable channel A,B,C,D. Here we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * clear the bit 31 of register REG_ADC_CH_A\B\C\D_CFG1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tmp_cfg1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) readl(info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp_cfg1 &= ~IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(tmp_cfg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) adc_analogure_clk = imx7d_adc_analogue_clk[adc_feature->clk_pre_div];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sample_rate |= adc_analogure_clk.reg_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) info->pre_div_num = adc_analogure_clk.pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sample_rate |= adc_feature->core_time_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(sample_rate, info->regs + IMX7D_REG_ADC_TIMER_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void imx7d_adc_hw_init(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* power up and enable adc analogue core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cfg &= ~(IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* enable channel A,B,C,D interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) info->regs + IMX7D_REG_ADC_INT_SIG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) info->regs + IMX7D_REG_ADC_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) imx7d_adc_sample_rate_set(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void imx7d_adc_channel_set(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 cfg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 cfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) channel = info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* the channel choose single conversion, and enable average mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * physical channel 0 chose logical channel A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * physical channel 1 chose logical channel B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * physical channel 2 chose logical channel C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * physical channel 3 chose logical channel D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * read register REG_ADC_CH_A\B\C\D_CFG2, according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * channel chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * write the register REG_ADC_CH_A\B\C\D_CFG2, according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * the channel chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static u32 imx7d_adc_get_sample_rate(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 analogue_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 core_time_unit = info->adc_feature.core_time_unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) analogue_core_clk = IMX7D_ADC_INPUT_CLK / info->pre_div_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tmp = (core_time_unit + 1) * 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return analogue_core_clk / tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int imx7d_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct imx7d_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) channel = chan->channel & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) info->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) imx7d_adc_channel_set(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = wait_for_completion_interruptible_timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (&info->completion, IMX7D_ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *val = info->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) info->vref_uv = regulator_get_voltage(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *val = info->vref_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *val2 = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *val = imx7d_adc_get_sample_rate(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int imx7d_adc_read_data(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) channel = info->channel & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * channel A and B conversion result share one register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * bit[27~16] is the channel B conversion result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * bit[11~0] is the channel A conversion result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * channel C and D is the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (channel < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) value = readl(info->regs + IMX7D_REG_ADC_CHA_B_CNV_RSLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) value = readl(info->regs + IMX7D_REG_ADC_CHC_D_CNV_RSLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (channel & 0x1) /* channel B or D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) value = (value >> 16) & 0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) else /* channel A or C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) value &= 0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static irqreturn_t imx7d_adc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct imx7d_adc *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) status = readl(info->regs + IMX7D_REG_ADC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) info->value = imx7d_adc_read_data(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * The register IMX7D_REG_ADC_INT_STATUS can't clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * itself after read operation, need software to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * 0 to the related bit. Here we clear the channel A/B/C/D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * conversion finished flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * If the channel A/B/C/D conversion timeout, report it and clear these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * timeout flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "ADC got conversion time out interrupt: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int imx7d_adc_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned reg, unsigned writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct imx7d_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!readval || reg % 4 || reg > IMX7D_REG_ADC_ADC_CFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *readval = readl(info->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const struct iio_info imx7d_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .read_raw = &imx7d_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .debugfs_reg_access = &imx7d_adc_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct of_device_id imx7d_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { .compatible = "fsl,imx7d-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MODULE_DEVICE_TABLE(of, imx7d_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void imx7d_adc_power_down(struct imx7d_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 adc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) adc_cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) adc_cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) adc_cfg &= ~IMX7D_REG_ADC_ADC_CFG_ADC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(adc_cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int imx7d_adc_enable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct imx7d_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = regulator_enable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "Can't enable adc reference top voltage, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "Could not prepare or enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) imx7d_adc_hw_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int imx7d_adc_disable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct imx7d_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) imx7d_adc_power_down(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regulator_disable(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void __imx7d_adc_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) imx7d_adc_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int imx7d_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct imx7d_adc *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(&pdev->dev, "Failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) info->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) info->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (IS_ERR(info->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return PTR_ERR(info->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) info->clk = devm_clk_get(dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(dev, "Failed getting clock, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) info->vref = devm_regulator_get(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(info->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = PTR_ERR(info->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "Failed getting reference voltage, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) init_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) indio_dev->info = &imx7d_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) indio_dev->channels = imx7d_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) indio_dev->num_channels = ARRAY_SIZE(imx7d_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = devm_request_irq(dev, irq, imx7d_adc_isr, 0, dev_name(dev), info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) imx7d_adc_feature_config(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = imx7d_adc_enable(&indio_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = devm_add_action_or_reset(dev, __imx7d_adc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &indio_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_err(&pdev->dev, "Couldn't register the device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable, imx7d_adc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static struct platform_driver imx7d_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .probe = imx7d_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .name = "imx7d_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .of_match_table = imx7d_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .pm = &imx7d_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) module_platform_driver(imx7d_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MODULE_DESCRIPTION("Freescale IMX7D ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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