^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HX711: analog to digital converter for weight sensor module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Andreas Klinger <ak@it-klinger.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* gain to pulse and scale conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HX711_GAIN_MAX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HX711_RESET_GAIN 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct hx711_gain_to_scale {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int gain_pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * .scale depends on AVDD which in turn is known as soon as the regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * therefore we set .scale in hx711_probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * channel A in documentation is channel 0 in source code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * channel B in documentation is channel 1 in source code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct hx711_gain_to_scale hx711_gain_to_scale[HX711_GAIN_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 128, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 32, 2, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 64, 3, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int hx711_get_gain_to_pulse(int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) for (i = 0; i < HX711_GAIN_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (hx711_gain_to_scale[i].gain == gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return hx711_gain_to_scale[i].gain_pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int hx711_get_gain_to_scale(int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) for (i = 0; i < HX711_GAIN_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (hx711_gain_to_scale[i].gain == gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return hx711_gain_to_scale[i].scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int hx711_get_scale_to_gain(int scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for (i = 0; i < HX711_GAIN_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (hx711_gain_to_scale[i].scale == scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return hx711_gain_to_scale[i].gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct hx711_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct gpio_desc *gpiod_pd_sck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct gpio_desc *gpiod_dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct regulator *reg_avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int gain_set; /* gain set on device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int gain_chan_a; /* gain for channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * triggered buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 2x32-bit channel + 64-bit naturally aligned timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 buffer[4] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * delay after a rising edge on SCK until the data is ready DOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * this is dependent on the hx711 where the datasheet tells a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * maximum value of 100 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * but also on potential parasitic capacities on the wiring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 data_ready_delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 clock_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int hx711_cycle(struct hx711_data *hx711_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * if preempted for more then 60us while PD_SCK is high:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * hx711 is going in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * ==> measuring is false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * wait until DOUT is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * it turned out that parasitic capacities are extending the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * until DOUT has reached it's value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ndelay(hx711_data->data_ready_delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * here we are not waiting for 0.2 us as suggested by the datasheet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * because the oscilloscope showed in a test scenario
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * at least 1.15 us for PD_SCK high (T3 in datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * and 0.56 us for PD_SCK low on TI Sitara with 800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * make it a square wave for addressing cases with capacitance on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * PC_SCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ndelay(hx711_data->data_ready_delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* sample as late as possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return gpiod_get_value(hx711_data->gpiod_dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int hx711_read(struct hx711_data *hx711_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int val = gpiod_get_value(hx711_data->gpiod_dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* we double check if it's really down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (i = 0; i < 24; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) value <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = hx711_cycle(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) value++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) value ^= 0x800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) for (i = 0; i < hx711_get_gain_to_pulse(hx711_data->gain_set); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) hx711_cycle(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int hx711_wait_for_ready(struct hx711_data *hx711_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int i, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * in some rare cases the reset takes quite a long time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * especially when the channel is changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Allow up to one second for it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = gpiod_get_value(hx711_data->gpiod_dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* sleep at least 10 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int hx711_reset(struct hx711_data *hx711_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int val = hx711_wait_for_ready(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * an examination with the oszilloscope indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * that the first value read after the reset is not stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * if we reset too short;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * the shorter the reset cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * the less reliable the first value after reset is;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * there were no problems encountered with a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * of 10 ms or higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val = hx711_wait_for_ready(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* after a reset the gain is 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) hx711_data->gain_set = HX711_RESET_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int hx711_set_gain_for_channel(struct hx711_data *hx711_data, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (chan == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (hx711_data->gain_set == 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) hx711_data->gain_set = hx711_data->gain_chan_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = hx711_read(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = hx711_wait_for_ready(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (hx711_data->gain_set != 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) hx711_data->gain_set = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = hx711_read(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = hx711_wait_for_ready(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int hx711_reset_read(struct hx711_data *hx711_data, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * hx711_reset() must be called from here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * because it could be calling hx711_read() by itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (hx711_reset(hx711_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(hx711_data->dev, "reset failed!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = hx711_set_gain_for_channel(hx711_data, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val = hx711_read(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int hx711_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct hx711_data *hx711_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mutex_lock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *val = hx711_reset_read(hx711_data, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mutex_unlock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mutex_lock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *val2 = hx711_get_gain_to_scale(hx711_data->gain_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mutex_unlock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int hx711_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct hx711_data *hx711_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * a scale greater than 1 mV per LSB is not possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * with the HX711, therefore val must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mutex_lock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) gain = hx711_get_scale_to_gain(val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (gain < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mutex_unlock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (gain != hx711_data->gain_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hx711_data->gain_set = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (gain != 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) hx711_data->gain_chan_a = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = hx711_read(hx711_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mutex_unlock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mutex_unlock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int hx711_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static irqreturn_t hx711_trigger(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct hx711_data *hx711_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int i, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mutex_lock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) memset(hx711_data->buffer, 0, sizeof(hx711_data->buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for (i = 0; i < indio_dev->masklength; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!test_bit(i, indio_dev->active_scan_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hx711_data->buffer[j] = hx711_reset_read(hx711_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) indio_dev->channels[i].channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) iio_push_to_buffers_with_timestamp(indio_dev, hx711_data->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mutex_unlock(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static ssize_t hx711_scale_available_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int channel = iio_attr->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) for (i = 0; i < HX711_GAIN_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (hx711_gain_to_scale[i].channel == channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) len += sprintf(buf + len, "0.%09d ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hx711_gain_to_scale[i].scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) len += sprintf(buf + len, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hx711_scale_available_show, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static IIO_DEVICE_ATTR(in_voltage1_scale_available, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) hx711_scale_available_show, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct attribute *hx711_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct attribute_group hx711_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .attrs = hx711_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct iio_info hx711_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .read_raw = hx711_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .write_raw = hx711_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .write_raw_get_fmt = hx711_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .attrs = &hx711_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct iio_chan_spec hx711_chan_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .scan_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .realbits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .storagebits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .endianness = IIO_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .channel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .scan_index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .realbits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .storagebits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .endianness = IIO_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) IIO_CHAN_SOFT_TIMESTAMP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int hx711_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct hx711_data *hx711_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) indio_dev = devm_iio_device_alloc(dev, sizeof(struct hx711_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(dev, "failed to allocate IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hx711_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hx711_data->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mutex_init(&hx711_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * PD_SCK stands for power down and serial clock input of HX711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * in the driver it is an output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hx711_data->gpiod_pd_sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (IS_ERR(hx711_data->gpiod_pd_sck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(dev, "failed to get sck-gpiod: err=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PTR_ERR(hx711_data->gpiod_pd_sck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return PTR_ERR(hx711_data->gpiod_pd_sck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * DOUT stands for serial data output of HX711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * for the driver it is an input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) hx711_data->gpiod_dout = devm_gpiod_get(dev, "dout", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (IS_ERR(hx711_data->gpiod_dout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(dev, "failed to get dout-gpiod: err=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PTR_ERR(hx711_data->gpiod_dout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return PTR_ERR(hx711_data->gpiod_dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hx711_data->reg_avdd = devm_regulator_get(dev, "avdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (IS_ERR(hx711_data->reg_avdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return PTR_ERR(hx711_data->reg_avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = regulator_enable(hx711_data->reg_avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * full scale differential input range: AVDD / GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * full scale output data: 2^24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * we can say:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * AVDD / GAIN = 2^24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * therefore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * 1 LSB = AVDD / GAIN / 2^24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * AVDD is in uV, but we need 10^-9 mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * approximately to fit into a 32 bit number:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * 1 LSB = (AVDD * 100) / GAIN / 1678 [10^-9 mV]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = regulator_get_voltage(hx711_data->reg_avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto error_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* we need 10^-9 mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret *= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) for (i = 0; i < HX711_GAIN_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hx711_gain_to_scale[i].scale =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret / hx711_gain_to_scale[i].gain / 1678;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hx711_data->gain_set = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hx711_data->gain_chan_a = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hx711_data->clock_frequency = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = of_property_read_u32(np, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) &hx711_data->clock_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * datasheet says the high level of PD_SCK has a maximum duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * of 50 microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (hx711_data->clock_frequency < 20000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_warn(dev, "clock-frequency too low - assuming 400 kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hx711_data->clock_frequency = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) hx711_data->data_ready_delay_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 1000000000 / hx711_data->clock_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) indio_dev->name = "hx711";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) indio_dev->info = &hx711_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) indio_dev->channels = hx711_chan_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) indio_dev->num_channels = ARRAY_SIZE(hx711_chan_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) hx711_trigger, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(dev, "setup of iio triggered buffer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) goto error_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(dev, "Couldn't register the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto error_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) error_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) error_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) regulator_disable(hx711_data->reg_avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int hx711_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct hx711_data *hx711_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hx711_data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) regulator_disable(hx711_data->reg_avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const struct of_device_id of_hx711_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .compatible = "avia,hx711", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_DEVICE_TABLE(of, of_hx711_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct platform_driver hx711_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .probe = hx711_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .remove = hx711_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .name = "hx711-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .of_match_table = of_hx711_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) module_platform_driver(hx711_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MODULE_AUTHOR("Andreas Klinger <ak@it-klinger.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MODULE_DESCRIPTION("HX711 bitbanging driver - ADC for weight cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MODULE_ALIAS("platform:hx711-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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