^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Ziyuan Xu <xzy.xu@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * id: the index of analog switch inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * saradc_chan_id: the index of analog switch 'x' output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * gpio_mask: set the value of switch-gpios with mask, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * makes the 'id' connect to 'saradc_chan_id'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct gpio_muxadc_chan_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 saradc_chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MUXADC_CHANNEL(_index, _id, _mask) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .id = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .saradc_chan_id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .gpio_mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * nr_chans: the number of analog switch 'x' output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * saradc_nr_chans: the number of analog switch inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * chans: pointer to get the muxadc channel information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct gpio_muxadc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 saradc_nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct gpio_muxadc_chan_data *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * gpios: pointer of digital enable input gpios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * adc_chans: pointer of the 'saraadc' channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * muxchans: specification of a single analog switch 'x'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * output channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * data: pointer to get the muxadc channels information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * nr_chans: the number of analog switch 'x' output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct gpio_muxadc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct gpio_descs *gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct iio_channel *adc_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct iio_chan_spec *muxchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct gpio_muxadc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int gpio_muxadc_chan_read_by_index(struct gpio_muxadc *muxadc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int index, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct iio_channel *saradc_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const struct gpio_muxadc_chan_data *chan_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 i, saradc_chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) chan_data = &muxadc->data->chans[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (i = 0; i < muxadc->gpios->ndescs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct gpio_desc *gpiod = muxadc->gpios->desc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int gpio_val = chan_data->gpio_mask & BIT(i) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) gpiod_set_value(gpiod, gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) saradc_chan_id = chan_data->saradc_chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) saradc_chan = &muxadc->adc_chans[saradc_chan_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return iio_read_channel_raw(saradc_chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int gpio_muxadc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct gpio_muxadc *muxadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = gpio_muxadc_chan_read_by_index(muxadc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct iio_info gpio_muxadc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .read_raw = gpio_muxadc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct gpio_muxadc_chan_data mux_sgm3699_chans_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUXADC_CHANNEL(0, 0, 0b00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MUXADC_CHANNEL(1, 1, 0b00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MUXADC_CHANNEL(2, 2, 0b00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUXADC_CHANNEL(3, 3, 0b00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUXADC_CHANNEL(4, 0, 0b01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MUXADC_CHANNEL(5, 1, 0b01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUXADC_CHANNEL(6, 2, 0b11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUXADC_CHANNEL(7, 3, 0b11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct gpio_muxadc_data mux_sgm3699_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .saradc_nr_chans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .nr_chans = ARRAY_SIZE(mux_sgm3699_chans_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .chans = mux_sgm3699_chans_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct gpio_muxadc_chan_data mux_sgm48752_chans_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUXADC_CHANNEL(0, 0, 0b00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUXADC_CHANNEL(1, 1, 0b00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUXADC_CHANNEL(2, 0, 0b10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MUXADC_CHANNEL(3, 1, 0b10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUXADC_CHANNEL(4, 0, 0b01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUXADC_CHANNEL(5, 1, 0b01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MUXADC_CHANNEL(6, 0, 0b11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MUXADC_CHANNEL(7, 1, 0b11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct gpio_muxadc_data mux_sgm48752_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .saradc_nr_chans = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .nr_chans = ARRAY_SIZE(mux_sgm48752_chans_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .chans = mux_sgm48752_chans_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct of_device_id of_gpio_muxadc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .compatible = "sgm3699",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .data = &mux_sgm3699_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .compatible = "sgm48752",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .data = &mux_sgm48752_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_DEVICE_TABLE(of, of_gpio_muxadc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int gpio_muxadc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct gpio_muxadc *muxadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 i, nr_adc_chans = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) indio_dev = devm_iio_device_alloc(dev, sizeof(*muxadc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) muxadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) match = of_match_device(of_gpio_muxadc_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(dev, "failed to match device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) muxadc->data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) muxadc->gpios = devm_gpiod_get_array(dev, "switch", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_ERR(muxadc->gpios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(dev, "property of switch-gpios not specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return PTR_ERR(muxadc->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) muxadc->adc_chans = iio_channel_get_all(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (IS_ERR(muxadc->adc_chans))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return PTR_ERR(muxadc->adc_chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * It's necessary to get the number of input ADC, and make a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * comparison with chan_data->saradc_nr_chans. Otherwise it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * might fall in to trap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) while (muxadc->adc_chans[nr_adc_chans].indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) nr_adc_chans++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (muxadc->data->saradc_nr_chans != nr_adc_chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(dev, "the number of io-channels is mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) muxadc->nr_chans = of_property_count_strings(np, "labels");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (muxadc->nr_chans != muxadc->data->nr_chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(dev, "should provide %d label\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) muxadc->nr_chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) muxadc->muxchans = devm_kcalloc(dev, muxadc->nr_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sizeof(struct iio_chan_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!muxadc->muxchans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for (i = 0; i < muxadc->nr_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * The specification of each muxadc channel will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * in_voltage_<label> without been indexed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) muxadc->muxchans[i].type = IIO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) muxadc->muxchans[i].channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) muxadc->muxchans[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) of_property_read_string_index(np, "labels", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &muxadc->muxchans[i].extend_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) indio_dev->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) indio_dev->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) indio_dev->info = &gpio_muxadc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) indio_dev->channels = muxadc->muxchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) indio_dev->num_channels = muxadc->nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int gpio_muxadc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct platform_driver gpio_muxadc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .probe = gpio_muxadc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .remove = gpio_muxadc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "gpio-muxadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .of_match_table = of_gpio_muxadc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) module_platform_driver(gpio_muxadc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_AUTHOR("Ziyuan Xu <xzy.xu@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_DESCRIPTION("GPIO MUX ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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