Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This is the driver for the imx25 GCQ (Generic Conversion Queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * connected to the imx25 ADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <dt-bindings/iio/adc/fsl-imx25-gcq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/imx25-tsadc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MX25_GCQ_TIMEOUT (msecs_to_jiffies(2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static const char * const driver_name = "mx25-gcq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) enum mx25_gcq_cfgs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	MX25_CFG_XP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	MX25_CFG_YP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	MX25_CFG_XN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	MX25_CFG_YN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	MX25_CFG_WIPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	MX25_CFG_INAUX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	MX25_CFG_INAUX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	MX25_CFG_INAUX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	MX25_NUM_CFGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct mx25_gcq_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct regmap *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct completion completed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct regulator *vref[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 channel_vref_mv[MX25_NUM_CFGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 * Lock to protect the device state during a potential concurrent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 * read access from userspace. Reading a raw value requires a sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 * of register writes, then a wait for a completion callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * and finally a register read, during which userspace could issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * another read request. This lock protects a read access from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * ocurring before another one has finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MX25_CQG_CHAN(chan, id) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.type = IIO_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.indexed = 1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.channel = chan,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			      BIT(IIO_CHAN_INFO_SCALE),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.datasheet_name = id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct iio_chan_spec mx25_gcq_channels[MX25_NUM_CFGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MX25_CQG_CHAN(MX25_CFG_XP, "xp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MX25_CQG_CHAN(MX25_CFG_YP, "yp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	MX25_CQG_CHAN(MX25_CFG_XN, "xn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	MX25_CQG_CHAN(MX25_CFG_YN, "yn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	MX25_CQG_CHAN(MX25_CFG_WIPER, "wiper"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	MX25_CQG_CHAN(MX25_CFG_INAUX0, "inaux0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	MX25_CQG_CHAN(MX25_CFG_INAUX1, "inaux1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MX25_CQG_CHAN(MX25_CFG_INAUX2, "inaux2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static const char * const mx25_gcq_refp_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[MX25_ADC_REFP_YP] = "yp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[MX25_ADC_REFP_XP] = "xp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[MX25_ADC_REFP_INT] = "int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	[MX25_ADC_REFP_EXT] = "ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static irqreturn_t mx25_gcq_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct mx25_gcq_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	regmap_read(priv->regs, MX25_ADCQ_SR, &stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (stats & MX25_ADCQ_SR_EOQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		regmap_update_bits(priv->regs, MX25_ADCQ_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				   MX25_ADCQ_MR_EOQ_IRQ, MX25_ADCQ_MR_EOQ_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		complete(&priv->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Disable conversion queue run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* Acknowledge all possible irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	regmap_write(priv->regs, MX25_ADCQ_SR, MX25_ADCQ_SR_FRR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		     MX25_ADCQ_SR_FUR | MX25_ADCQ_SR_FOR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		     MX25_ADCQ_SR_EOQ | MX25_ADCQ_SR_PD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int mx25_gcq_get_raw_value(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				  struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				  struct mx25_gcq_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				  int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Setup the configuration we want to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	regmap_write(priv->regs, MX25_ADCQ_ITEM_7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		     MX25_ADCQ_ITEM(0, chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	regmap_update_bits(priv->regs, MX25_ADCQ_MR, MX25_ADCQ_MR_EOQ_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* Trigger queue for one run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	regmap_update_bits(priv->regs, MX25_ADCQ_CR, MX25_ADCQ_CR_FQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			   MX25_ADCQ_CR_FQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	timeout = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		&priv->completed, MX25_GCQ_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (timeout < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		dev_err(dev, "ADC wait for measurement failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	} else if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		dev_err(dev, "ADC timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	regmap_read(priv->regs, MX25_ADCQ_FIFO, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	*val = MX25_ADCQ_FIFO_DATA(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int mx25_gcq_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			     struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			     int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct mx25_gcq_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ret = mx25_gcq_get_raw_value(&indio_dev->dev, chan, priv, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		*val = priv->channel_vref_mv[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		*val2 = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct iio_info mx25_gcq_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.read_raw = mx25_gcq_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct regmap_config mx25_gcq_regconfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.max_register = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int mx25_gcq_setup_cfgs(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			       struct mx25_gcq_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned int refp_used[4] = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * Setup all configurations registers with a default conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * configuration for each input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	for (i = 0; i < MX25_NUM_CFGS; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		regmap_write(priv->regs, MX25_ADCQ_CFG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			     MX25_ADCQ_CFG_YPLL_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			     MX25_ADCQ_CFG_XNUR_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			     MX25_ADCQ_CFG_XPUL_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			     MX25_ADCQ_CFG_REFP_INT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			     MX25_ADCQ_CFG_IN(i) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			     MX25_ADCQ_CFG_REFN_NGND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * First get all regulators to store them in channel_vref_mv if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * necessary. Later we use that information for proper IIO scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	priv->vref[MX25_ADC_REFP_INT] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	priv->vref[MX25_ADC_REFP_EXT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		devm_regulator_get_optional(&pdev->dev, "vref-ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	priv->vref[MX25_ADC_REFP_XP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		devm_regulator_get_optional(&pdev->dev, "vref-xp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	priv->vref[MX25_ADC_REFP_YP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		devm_regulator_get_optional(&pdev->dev, "vref-yp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		u32 refp = MX25_ADCQ_CFG_REFP_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		u32 refn = MX25_ADCQ_CFG_REFN_NGND2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret = of_property_read_u32(child, "reg", &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			dev_err(dev, "Failed to get reg property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (reg >= MX25_NUM_CFGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				"reg value is greater than the number of available configuration registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		of_property_read_u32(child, "fsl,adc-refp", &refp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		of_property_read_u32(child, "fsl,adc-refn", &refn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		switch (refp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		case MX25_ADC_REFP_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		case MX25_ADC_REFP_XP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		case MX25_ADC_REFP_YP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			if (IS_ERR(priv->vref[refp])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				dev_err(dev, "Error, trying to use external voltage reference without a vref-%s regulator.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					mx25_gcq_refp_names[refp]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				return PTR_ERR(priv->vref[refp]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			priv->channel_vref_mv[reg] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				regulator_get_voltage(priv->vref[refp]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			/* Conversion from uV to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			priv->channel_vref_mv[reg] /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		case MX25_ADC_REFP_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			priv->channel_vref_mv[reg] = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			dev_err(dev, "Invalid positive reference %d\n", refp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		++refp_used[refp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		 * Shift the read values to the correct positions within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		 * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		refp = MX25_ADCQ_CFG_REFP(refp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		refn = MX25_ADCQ_CFG_REFN(refn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		if ((refp & MX25_ADCQ_CFG_REFP_MASK) != refp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			dev_err(dev, "Invalid fsl,adc-refp property value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if ((refn & MX25_ADCQ_CFG_REFN_MASK) != refn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			dev_err(dev, "Invalid fsl,adc-refn property value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		regmap_update_bits(priv->regs, MX25_ADCQ_CFG(reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				   MX25_ADCQ_CFG_REFP_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				   MX25_ADCQ_CFG_REFN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				   refp | refn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	regmap_update_bits(priv->regs, MX25_ADCQ_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			   MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			   MX25_ADCQ_CR_FRST | MX25_ADCQ_CR_QRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	regmap_write(priv->regs, MX25_ADCQ_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		     MX25_ADCQ_CR_PDMSK | MX25_ADCQ_CR_QSM_FQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/* Remove unused regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	for (i = 0; i != 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		if (!refp_used[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			if (!IS_ERR_OR_NULL(priv->vref[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				devm_regulator_put(priv->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			priv->vref[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int mx25_gcq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct mx25_gcq_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct mx25_tsadc *tsadc = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	void __iomem *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	mem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (IS_ERR(mem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return PTR_ERR(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	priv->regs = devm_regmap_init_mmio(dev, mem, &mx25_gcq_regconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (IS_ERR(priv->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(dev, "Failed to initialize regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return PTR_ERR(priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	init_completion(&priv->completed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = mx25_gcq_setup_cfgs(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	for (i = 0; i != 4; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		if (!priv->vref[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ret = regulator_enable(priv->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			goto err_regulator_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	priv->clk = tsadc->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		dev_err(dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		goto err_vref_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	priv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (priv->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		ret = priv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	ret = request_irq(priv->irq, mx25_gcq_irq, 0, pdev->name, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		dev_err(dev, "Failed requesting IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	indio_dev->channels = mx25_gcq_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	indio_dev->num_channels = ARRAY_SIZE(mx25_gcq_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	indio_dev->info = &mx25_gcq_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	indio_dev->name = driver_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		dev_err(dev, "Failed to register iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		goto err_irq_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) err_irq_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	free_irq(priv->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) err_clk_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err_vref_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	i = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err_regulator_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	for (; i-- > 0;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (priv->vref[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			regulator_disable(priv->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int mx25_gcq_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct mx25_gcq_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	free_irq(priv->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	for (i = 4; i-- > 0;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		if (priv->vref[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			regulator_disable(priv->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct of_device_id mx25_gcq_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	{ .compatible = "fsl,imx25-gcq", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	{ /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_DEVICE_TABLE(of, mx25_gcq_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct platform_driver mx25_gcq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.name	= "mx25-gcq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.of_match_table = mx25_gcq_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.probe		= mx25_gcq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.remove		= mx25_gcq_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) module_platform_driver(mx25_gcq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_DESCRIPTION("ADC driver for Freescale mx25");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_LICENSE("GPL v2");