^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * exynos_adc.c - Support for ADC in EXYNOS SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 8 ~ 10 channel, 10/12-bit ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_data/touchscreen-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADC_V1_CON(x) ((x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADC_V1_TSC(x) ((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADC_V1_DLY(x) ((x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ADC_V1_DATX(x) ((x) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ADC_V1_DATY(x) ((x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ADC_V1_UPDN(x) ((x) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ADC_V1_INTCLR(x) ((x) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ADC_V1_MUX(x) ((x) + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ADC_V1_CLRINTPNDNUP(x) ((x) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* S3C2410 ADC registers definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ADC_S3C2410_MUX(x) ((x) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Future ADC_V2 registers definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ADC_V2_CON1(x) ((x) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ADC_V2_CON2(x) ((x) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ADC_V2_STAT(x) ((x) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ADC_V2_INT_EN(x) ((x) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ADC_V2_INT_ST(x) ((x) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADC_V2_VER(x) ((x) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Bit definitions for ADC_V1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ADC_V1_CON_RES (1u << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ADC_V1_CON_PRSCEN (1u << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ADC_V1_CON_STANDBY (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Bit definitions for S3C2410 ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ADC_S3C2410_DATX_MASK 0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ADC_S3C2416_CON_RES_SEL (1u << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* touch screen always uses channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ADC_S3C2410_MUX_TS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* ADCTSC Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ADC_S3C2443_TSC_UD_SEN (1u << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ADC_S3C2410_TSC_YM_SEN (1u << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ADC_S3C2410_TSC_YP_SEN (1u << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ADC_S3C2410_TSC_XM_SEN (1u << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ADC_S3C2410_TSC_XP_SEN (1u << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADC_S3C2410_TSC_AUTO_PST (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADC_S3C2410_TSC_XY_PST(x) (((x) & 0x3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ADC_S3C2410_TSC_YP_SEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ADC_S3C2410_TSC_XP_SEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ADC_S3C2410_TSC_XY_PST(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ADC_S3C2410_TSC_YP_SEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ADC_S3C2410_TSC_XP_SEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ADC_S3C2410_TSC_AUTO_PST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ADC_S3C2410_TSC_XY_PST(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Bit definitions for ADC_V2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADC_V2_CON1_SOFT_RESET (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ADC_V2_CON2_OSEL (1u << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ADC_V2_CON2_ESEL (1u << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ADC_V2_CON2_HIGHF (1u << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ADC_V2_CON2_ACH_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX_ADC_V2_CHANNELS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAX_ADC_V1_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAX_EXYNOS3250_ADC_CHANNELS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAX_EXYNOS4212_ADC_CHANNELS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MAX_S5PV210_ADC_CHANNELS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Bit definitions common for ADC_V1 and ADC_V2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ADC_CON_EN_START (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADC_CON_EN_START_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADC_DATX_PRESSED (1u << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADC_DATX_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADC_DATY_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EXYNOS_ADCV1_PHY_OFFSET 0x0718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EXYNOS_ADCV2_PHY_OFFSET 0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct exynos_adc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct exynos_adc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct input_dev *input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct regmap *pmu_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int tsirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool read_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 ts_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 ts_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Lock to protect from potential concurrent access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * completion callback during a manual conversion. For this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * a wait-callback is used to wait for the conversion result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * so in the meantime no other read request (or conversion start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * must be performed, otherwise it would interfere with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * current conversion result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct exynos_adc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool needs_sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool needs_adc_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int phy_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void (*init_hw)(struct exynos_adc *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void (*exit_hw)(struct exynos_adc *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void (*clear_irq)(struct exynos_adc *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void (*start_conv)(struct exynos_adc *info, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void exynos_adc_unprepare_clk(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (info->data->needs_sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk_unprepare(info->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int exynos_adc_prepare_clk(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = clk_prepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (info->data->needs_sclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = clk_prepare(info->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) clk_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "failed preparing sclk_adc clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void exynos_adc_disable_clk(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (info->data->needs_sclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_disable(info->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk_disable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int exynos_adc_enable_clk(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = clk_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (info->data->needs_sclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = clk_enable(info->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) clk_disable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "failed enabling sclk_adc clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void exynos_adc_v1_init_hw(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 con1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (info->data->needs_adc_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) regmap_write(info->pmu_map, info->data->phy_offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* set default prescaler values and Enable prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Enable 12-bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) con1 |= ADC_V1_CON_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(con1, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* set touchscreen delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel(info->delay, ADC_V1_DLY(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (info->data->needs_adc_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) regmap_write(info->pmu_map, info->data->phy_offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) con = readl(ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) con |= ADC_V1_CON_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(con, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(1, ADC_V1_INTCLR(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void exynos_adc_v1_start_conv(struct exynos_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 con1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(addr, ADC_V1_MUX(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) con1 = readl(ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Exynos4212 and 4412 is like ADCv1 but with four channels only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct exynos_adc_data exynos4212_adc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .num_channels = MAX_EXYNOS4212_ADC_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .needs_adc_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .clear_irq = exynos_adc_v1_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .start_conv = exynos_adc_v1_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct exynos_adc_data exynos_adc_v1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .num_channels = MAX_ADC_V1_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .needs_adc_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .clear_irq = exynos_adc_v1_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .start_conv = exynos_adc_v1_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct exynos_adc_data exynos_adc_s5pv210_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .num_channels = MAX_S5PV210_ADC_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .clear_irq = exynos_adc_v1_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .start_conv = exynos_adc_v1_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 con1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Enable 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) con1 = readl(ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) con1 |= ADC_S3C2416_CON_RES_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(con1, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Select channel for S3C2416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(addr, ADC_S3C2410_MUX(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) con1 = readl(ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct exynos_adc_data const exynos_adc_s3c2416_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .num_channels = MAX_ADC_V1_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .start_conv = exynos_adc_s3c2416_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 con1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Select channel for S3C2433 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(addr, ADC_S3C2410_MUX(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) con1 = readl(ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct exynos_adc_data const exynos_adc_s3c2443_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_channels = MAX_ADC_V1_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .start_conv = exynos_adc_s3c2443_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 con1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) con1 = readl(ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) con1 |= ADC_S3C2410_CON_SELMUX(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .num_channels = MAX_ADC_V1_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .start_conv = exynos_adc_s3c64xx_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .num_channels = MAX_ADC_V1_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .init_hw = exynos_adc_v1_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .exit_hw = exynos_adc_v1_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .clear_irq = exynos_adc_v1_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .start_conv = exynos_adc_s3c64xx_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void exynos_adc_v2_init_hw(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 con1, con2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (info->data->needs_adc_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) regmap_write(info->pmu_map, info->data->phy_offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) con1 = ADC_V2_CON1_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel(con1, ADC_V2_CON1(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writel(con2, ADC_V2_CON2(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writel(1, ADC_V2_INT_EN(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (info->data->needs_adc_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) regmap_write(info->pmu_map, info->data->phy_offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) con = readl(ADC_V2_CON1(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) con &= ~ADC_CON_EN_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel(con, ADC_V2_CON1(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) writel(1, ADC_V2_INT_ST(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void exynos_adc_v2_start_conv(struct exynos_adc *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 con1, con2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) con2 = readl(ADC_V2_CON2(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) con2 &= ~ADC_V2_CON2_ACH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) con2 |= ADC_V2_CON2_ACH_SEL(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writel(con2, ADC_V2_CON2(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) con1 = readl(ADC_V2_CON1(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct exynos_adc_data exynos_adc_v2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .num_channels = MAX_ADC_V2_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .needs_adc_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .init_hw = exynos_adc_v2_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .exit_hw = exynos_adc_v2_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .clear_irq = exynos_adc_v2_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .start_conv = exynos_adc_v2_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct exynos_adc_data exynos3250_adc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .needs_sclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .needs_adc_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .init_hw = exynos_adc_v2_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .exit_hw = exynos_adc_v2_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .clear_irq = exynos_adc_v2_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .start_conv = exynos_adc_v2_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u32 con1, con2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) con1 = ADC_V2_CON1_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) writel(con1, ADC_V2_CON1(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) con2 = readl(ADC_V2_CON2(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) con2 &= ~ADC_V2_CON2_C_TIME(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) con2 |= ADC_V2_CON2_C_TIME(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writel(con2, ADC_V2_CON2(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) writel(1, ADC_V2_INT_EN(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct exynos_adc_data exynos7_adc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .num_channels = MAX_ADC_V1_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .init_hw = exynos_adc_exynos7_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .exit_hw = exynos_adc_v2_exit_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .clear_irq = exynos_adc_v2_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .start_conv = exynos_adc_v2_start_conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const struct of_device_id exynos_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .compatible = "samsung,s3c2410-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .data = &exynos_adc_s3c24xx_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .compatible = "samsung,s3c2416-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .data = &exynos_adc_s3c2416_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .compatible = "samsung,s3c2440-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .data = &exynos_adc_s3c24xx_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .compatible = "samsung,s3c2443-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .data = &exynos_adc_s3c2443_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .compatible = "samsung,s3c6410-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .data = &exynos_adc_s3c64xx_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .compatible = "samsung,s5pv210-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .data = &exynos_adc_s5pv210_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .compatible = "samsung,exynos4212-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .data = &exynos4212_adc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .compatible = "samsung,exynos-adc-v1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .data = &exynos_adc_v1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .compatible = "samsung,exynos-adc-v2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .data = &exynos_adc_v2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .compatible = "samsung,exynos3250-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .data = &exynos3250_adc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .compatible = "samsung,exynos7-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .data = &exynos7_adc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_DEVICE_TABLE(of, exynos_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) match = of_match_node(exynos_adc_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return (struct exynos_adc_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int exynos_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct exynos_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (mask == IIO_CHAN_INFO_SCALE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = regulator_get_voltage(info->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Regulator voltage is in uV, but need mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) *val2 = info->data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else if (mask != IIO_CHAN_INFO_RAW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Select the channel to be used and Trigger conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (info->data->start_conv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) info->data->start_conv(info, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) timeout = wait_for_completion_timeout(&info->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) EXYNOS_ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (info->data->init_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) info->data->init_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *val = info->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct exynos_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) info->read_ts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) reinit_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ADC_V1_TSC(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Select the ts channel to be used and Trigger conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) info->data->start_conv(info, ADC_S3C2410_MUX_TS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) timeout = wait_for_completion_timeout(&info->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) EXYNOS_ADC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (info->data->init_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) info->data->init_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) *x = info->ts_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) *y = info->ts_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) info->read_ts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct exynos_adc *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 mask = info->data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (info->read_ts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) info->ts_x = readl(ADC_V1_DATX(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) info->ts_y = readl(ADC_V1_DATY(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) info->value = readl(ADC_V1_DATX(info->regs)) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* clear irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (info->data->clear_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) info->data->clear_irq(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) complete(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Here we (ab)use a threaded interrupt handler to stay running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * for as long as the touchscreen remains pressed, we report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * a new event with the latest data and then sleep until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * next timer tick. This mirrors the behavior of the old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * driver, with much less code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct exynos_adc *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct iio_dev *dev = dev_get_drvdata(info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) bool pressed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) while (info->input->users) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = exynos_read_s3c64xx_ts(dev, &x, &y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pressed = x & y & ADC_DATX_PRESSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (!pressed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) input_report_key(info->input, BTN_TOUCH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) input_sync(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) input_report_key(info->input, BTN_TOUCH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) input_sync(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int exynos_adc_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned reg, unsigned writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct exynos_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (readval == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *readval = readl(info->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const struct iio_info exynos_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .read_raw = &exynos_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .debugfs_reg_access = &exynos_adc_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define ADC_CHANNEL(_index, _id) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .channel = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .address = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .datasheet_name = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct iio_chan_spec exynos_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ADC_CHANNEL(0, "adc0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ADC_CHANNEL(1, "adc1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ADC_CHANNEL(2, "adc2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ADC_CHANNEL(3, "adc3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ADC_CHANNEL(4, "adc4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ADC_CHANNEL(5, "adc5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ADC_CHANNEL(6, "adc6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ADC_CHANNEL(7, "adc7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ADC_CHANNEL(8, "adc8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ADC_CHANNEL(9, "adc9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int exynos_adc_remove_devices(struct device *dev, void *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int exynos_adc_ts_open(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct exynos_adc *info = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) enable_irq(info->tsirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void exynos_adc_ts_close(struct input_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct exynos_adc *info = input_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) disable_irq(info->tsirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int exynos_adc_ts_init(struct exynos_adc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (info->tsirq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) info->input = input_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!info->input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) info->input->name = "S3C24xx TouchScreen";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) info->input->id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) info->input->open = exynos_adc_ts_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) info->input->close = exynos_adc_ts_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) input_set_drvdata(info->input, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = input_register_device(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) input_free_device(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) disable_irq(info->tsirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) IRQF_ONESHOT, "touchscreen", info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) input_unregister_device(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int exynos_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct exynos_adc *info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct iio_dev *indio_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) bool has_ts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev_err(&pdev->dev, "failed allocating iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) info->data = exynos_adc_get_data(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!info->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) info->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (IS_ERR(info->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return PTR_ERR(info->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (info->data->needs_adc_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) info->pmu_map = syscon_regmap_lookup_by_phandle(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "samsung,syscon-phandle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (IS_ERR(info->pmu_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return PTR_ERR(info->pmu_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) info->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) info->tsirq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) init_completion(&info->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) info->clk = devm_clk_get(&pdev->dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PTR_ERR(info->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (info->data->needs_sclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) info->sclk = devm_clk_get(&pdev->dev, "sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (IS_ERR(info->sclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "failed getting sclk clock, err = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PTR_ERR(info->sclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return PTR_ERR(info->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) info->vdd = devm_regulator_get(&pdev->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (IS_ERR(info->vdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "failed getting regulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = regulator_enable(info->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ret = exynos_adc_prepare_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = exynos_adc_enable_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) goto err_unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) indio_dev->info = &exynos_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) indio_dev->channels = exynos_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) indio_dev->num_channels = info->data->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mutex_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = request_irq(info->irq, exynos_adc_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) 0, dev_name(&pdev->dev), info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) info->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (info->data->init_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) info->data->init_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* leave out any TS related code if unreachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (IS_REACHABLE(CONFIG_INPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) has_ts = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "has-touchscreen") || pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) info->delay = pdata->delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) info->delay = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (has_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = exynos_adc_ts_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto err_iio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_err(&pdev->dev, "failed adding child nodes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) goto err_of_populate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) err_of_populate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) device_for_each_child(&indio_dev->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) exynos_adc_remove_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (has_ts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) input_unregister_device(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) free_irq(info->tsirq, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) err_iio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) free_irq(info->irq, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (info->data->exit_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) info->data->exit_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) exynos_adc_disable_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) err_unprepare_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) exynos_adc_unprepare_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) err_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) regulator_disable(info->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int exynos_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct exynos_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) free_irq(info->tsirq, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) input_unregister_device(info->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) device_for_each_child(&indio_dev->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) exynos_adc_remove_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) free_irq(info->irq, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (info->data->exit_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) info->data->exit_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) exynos_adc_disable_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) exynos_adc_unprepare_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) regulator_disable(info->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int exynos_adc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct exynos_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (info->data->exit_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) info->data->exit_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) exynos_adc_disable_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) regulator_disable(info->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int exynos_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct exynos_adc *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = regulator_enable(info->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = exynos_adc_enable_clk(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (info->data->init_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) info->data->init_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) exynos_adc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) exynos_adc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static struct platform_driver exynos_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .probe = exynos_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .remove = exynos_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .name = "exynos-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .of_match_table = exynos_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .pm = &exynos_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) module_platform_driver(exynos_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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