^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DA9150 GPADC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Dialog Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/da9150/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/da9150/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum da9150_gpadc_hw_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DA9150_GPADC_HW_CHAN_GPIOA_2V = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DA9150_GPADC_HW_CHAN_GPIOA_2V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DA9150_GPADC_HW_CHAN_GPIOB_2V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DA9150_GPADC_HW_CHAN_GPIOB_2V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DA9150_GPADC_HW_CHAN_GPIOC_2V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DA9150_GPADC_HW_CHAN_GPIOC_2V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DA9150_GPADC_HW_CHAN_GPIOD_2V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DA9150_GPADC_HW_CHAN_GPIOD_2V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DA9150_GPADC_HW_CHAN_IBUS_SENSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DA9150_GPADC_HW_CHAN_IBUS_SENSE_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DA9150_GPADC_HW_CHAN_VBUS_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DA9150_GPADC_HW_CHAN_VBUS_DIV_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DA9150_GPADC_HW_CHAN_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DA9150_GPADC_HW_CHAN_ID_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DA9150_GPADC_HW_CHAN_VSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DA9150_GPADC_HW_CHAN_VSYS_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DA9150_GPADC_HW_CHAN_GPIOA_6V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DA9150_GPADC_HW_CHAN_GPIOA_6V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DA9150_GPADC_HW_CHAN_GPIOB_6V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DA9150_GPADC_HW_CHAN_GPIOB_6V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DA9150_GPADC_HW_CHAN_GPIOC_6V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DA9150_GPADC_HW_CHAN_GPIOC_6V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DA9150_GPADC_HW_CHAN_GPIOD_6V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DA9150_GPADC_HW_CHAN_GPIOD_6V_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DA9150_GPADC_HW_CHAN_VBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DA9150_GPADC_HW_CHAN_VBAT_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DA9150_GPADC_HW_CHAN_TBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DA9150_GPADC_HW_CHAN_TBAT_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DA9150_GPADC_HW_CHAN_TJUNC_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DA9150_GPADC_HW_CHAN_TJUNC_CORE_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DA9150_GPADC_HW_CHAN_TJUNC_OVP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DA9150_GPADC_HW_CHAN_TJUNC_OVP_,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum da9150_gpadc_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DA9150_GPADC_CHAN_GPIOA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DA9150_GPADC_CHAN_GPIOB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DA9150_GPADC_CHAN_GPIOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DA9150_GPADC_CHAN_GPIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DA9150_GPADC_CHAN_IBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DA9150_GPADC_CHAN_VBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DA9150_GPADC_CHAN_VSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DA9150_GPADC_CHAN_VBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DA9150_GPADC_CHAN_TBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DA9150_GPADC_CHAN_TJUNC_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DA9150_GPADC_CHAN_TJUNC_OVP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct da9150_gpadc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct da9150 *da9150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static irqreturn_t da9150_gpadc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct da9150_gpadc *gpadc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) complete(&gpadc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int da9150_gpadc_read_adc(struct da9150_gpadc *gpadc, int hw_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 result_regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mutex_lock(&gpadc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Set channel & enable measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) da9150_reg_write(gpadc->da9150, DA9150_GPADC_MAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (DA9150_GPADC_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) hw_chan << DA9150_GPADC_MUX_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Consume left-over completion from a previous timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) try_wait_for_completion(&gpadc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Check for actual completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) wait_for_completion_timeout(&gpadc->complete, msecs_to_jiffies(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Read result and status from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) da9150_bulk_read(gpadc->da9150, DA9150_GPADC_RES_A, 2, result_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mutex_unlock(&gpadc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Check to make sure device really has completed reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (result_regs[1] & DA9150_GPADC_RUN_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(gpadc->dev, "Timeout on channel %d of GPADC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) hw_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* LSBs - 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) result = (result_regs[1] & DA9150_GPADC_RES_L_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DA9150_GPADC_RES_L_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* MSBs - 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) result |= result_regs[0] << DA9150_GPADC_RES_L_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline int da9150_gpadc_gpio_6v_voltage_now(int raw_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Convert to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return (6 * ((raw_val * 1000) + 500)) / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline int da9150_gpadc_ibus_current_avg(int raw_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Convert to mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return (4 * ((raw_val * 1000) + 500)) / 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline int da9150_gpadc_vbus_21v_voltage_now(int raw_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Convert to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return (21 * ((raw_val * 1000) + 500)) / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline int da9150_gpadc_vsys_6v_voltage_now(int raw_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Convert to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return (3 * ((raw_val * 1000) + 500)) / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int da9150_gpadc_read_processed(struct da9150_gpadc *gpadc, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int hw_chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int raw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) raw_val = da9150_gpadc_read_adc(gpadc, hw_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (raw_val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return raw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case DA9150_GPADC_CHAN_GPIOA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case DA9150_GPADC_CHAN_GPIOB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case DA9150_GPADC_CHAN_GPIOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case DA9150_GPADC_CHAN_GPIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *val = da9150_gpadc_gpio_6v_voltage_now(raw_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case DA9150_GPADC_CHAN_IBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *val = da9150_gpadc_ibus_current_avg(raw_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case DA9150_GPADC_CHAN_VBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *val = da9150_gpadc_vbus_21v_voltage_now(raw_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case DA9150_GPADC_CHAN_VSYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *val = da9150_gpadc_vsys_6v_voltage_now(raw_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* No processing for other channels so return raw value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *val = raw_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int da9150_gpadc_read_scale(int channel, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case DA9150_GPADC_CHAN_VBAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *val = 2932;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *val2 = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case DA9150_GPADC_CHAN_TJUNC_CORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case DA9150_GPADC_CHAN_TJUNC_OVP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *val = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *val2 = 4420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int da9150_gpadc_read_offset(int channel, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case DA9150_GPADC_CHAN_VBAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *val = 1500000 / 2932;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case DA9150_GPADC_CHAN_TJUNC_CORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case DA9150_GPADC_CHAN_TJUNC_OVP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *val = -144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int da9150_gpadc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct da9150_gpadc *gpadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if ((chan->channel < DA9150_GPADC_CHAN_GPIOA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (chan->channel > DA9150_GPADC_CHAN_TJUNC_OVP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return da9150_gpadc_read_processed(gpadc, chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return da9150_gpadc_read_scale(chan->channel, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return da9150_gpadc_read_offset(chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct iio_info da9150_gpadc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .read_raw = &da9150_gpadc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) _ext_name) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .channel = DA9150_GPADC_CHAN_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .address = DA9150_GPADC_HW_CHAN_##_hw_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .info_mask_separate = chan_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .extend_name = _ext_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .datasheet_name = #_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DA9150_GPADC_CHANNEL_RAW(_id, _hw_id, _type, _ext_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) BIT(IIO_CHAN_INFO_RAW), _ext_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DA9150_GPADC_CHANNEL_SCALED(_id, _hw_id, _type, _ext_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) _ext_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DA9150_GPADC_CHANNEL_PROCESSED(_id, _hw_id, _type, _ext_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DA9150_GPADC_CHANNEL(_id, _hw_id, _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) BIT(IIO_CHAN_INFO_PROCESSED), _ext_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Supported channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct iio_chan_spec da9150_gpadc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DA9150_GPADC_CHANNEL_PROCESSED(GPIOA, GPIOA_6V, IIO_VOLTAGE, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DA9150_GPADC_CHANNEL_PROCESSED(GPIOB, GPIOB_6V, IIO_VOLTAGE, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DA9150_GPADC_CHANNEL_PROCESSED(GPIOC, GPIOC_6V, IIO_VOLTAGE, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DA9150_GPADC_CHANNEL_PROCESSED(GPIOD, GPIOD_6V, IIO_VOLTAGE, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DA9150_GPADC_CHANNEL_PROCESSED(IBUS, IBUS_SENSE, IIO_CURRENT, "ibus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DA9150_GPADC_CHANNEL_PROCESSED(VBUS, VBUS_DIV_, IIO_VOLTAGE, "vbus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DA9150_GPADC_CHANNEL_PROCESSED(VSYS, VSYS, IIO_VOLTAGE, "vsys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DA9150_GPADC_CHANNEL_SCALED(VBAT, VBAT, IIO_VOLTAGE, "vbat"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DA9150_GPADC_CHANNEL_RAW(TBAT, TBAT, IIO_VOLTAGE, "tbat"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DA9150_GPADC_CHANNEL_SCALED(TJUNC_CORE, TJUNC_CORE, IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "tjunc_core"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DA9150_GPADC_CHANNEL_SCALED(TJUNC_OVP, TJUNC_OVP, IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "tjunc_ovp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Default maps used by da9150-charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct iio_map da9150_gpadc_default_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .consumer_dev_name = "da9150-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .consumer_channel = "CHAN_IBUS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .adc_channel_label = "IBUS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .consumer_dev_name = "da9150-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .consumer_channel = "CHAN_VBUS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .adc_channel_label = "VBUS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .consumer_dev_name = "da9150-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .consumer_channel = "CHAN_TJUNC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .adc_channel_label = "TJUNC_CORE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .consumer_dev_name = "da9150-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .consumer_channel = "CHAN_VBAT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .adc_channel_label = "VBAT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int da9150_gpadc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct da9150 *da9150 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct da9150_gpadc *gpadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(&pdev->dev, "Failed to allocate IIO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) gpadc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) gpadc->da9150 = da9150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) gpadc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mutex_init(&gpadc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) init_completion(&gpadc->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) irq = platform_get_irq_byname(pdev, "GPADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = devm_request_threaded_irq(dev, irq, NULL, da9150_gpadc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) IRQF_ONESHOT, "GPADC", gpadc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(dev, "Failed to request IRQ %d: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = iio_map_array_register(indio_dev, da9150_gpadc_default_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(dev, "Failed to register IIO maps: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) indio_dev->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) indio_dev->info = &da9150_gpadc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) indio_dev->channels = da9150_gpadc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) indio_dev->num_channels = ARRAY_SIZE(da9150_gpadc_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(dev, "Failed to register IIO device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto iio_map_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) iio_map_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) iio_map_array_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int da9150_gpadc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) iio_map_array_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct platform_driver da9150_gpadc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "da9150-gpadc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .probe = da9150_gpadc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .remove = da9150_gpadc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) module_platform_driver(da9150_gpadc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_DESCRIPTION("GPADC Driver for DA9150");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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