^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2015 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CC10001_ADC_CONFIG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CC10001_ADC_START_CONV BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CC10001_ADC_MODE_SINGLE_CONV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CC10001_ADC_DDATA_OUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CC10001_ADC_EOC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CC10001_ADC_EOC_SET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CC10001_ADC_CHSEL_SAMPLED 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CC10001_ADC_POWER_DOWN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CC10001_ADC_POWER_DOWN_SET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CC10001_ADC_DEBUG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CC10001_ADC_DATA_COUNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CC10001_ADC_DATA_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CC10001_ADC_NUM_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CC10001_ADC_CH_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CC10001_INVALID_SAMPLED 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CC10001_MAX_POLL_COUNT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * As per device specification, wait six clock cycles after power-up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * activate START. Since adding two more clock cycles delay does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * impact the performance too much, we are adding two additional cycles delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * intentionally here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CC10001_WAIT_CYCLES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cc10001_adc_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk *adc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bool shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int start_delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int eoc_delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(val, adc_dev->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return readl(adc_dev->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ndelay(adc_dev->start_delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) CC10001_ADC_POWER_DOWN_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Channel selection and mode of operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val = val | CC10001_ADC_START_CONV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int poll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CC10001_ADC_EOC_SET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ndelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (poll_count++ == CC10001_MAX_POLL_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return CC10001_INVALID_SAMPLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) poll_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CC10001_ADC_CH_MASK) != channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ndelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (poll_count++ == CC10001_MAX_POLL_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return CC10001_INVALID_SAMPLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Read the 10 bit output register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CC10001_ADC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct cc10001_adc_device *adc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int scan_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool sample_invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) data = adc_dev->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mutex_lock(&adc_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!adc_dev->shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cc10001_adc_power_up(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Calculate delay step for eoc and sampled data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sample_invalid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) channel = indio_dev->channels[scan_idx].channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cc10001_adc_start(adc_dev, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (data[i] == CC10001_INVALID_SAMPLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_warn(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "invalid sample on channel %d\n", channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sample_invalid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!adc_dev->shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cc10001_adc_power_down(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_unlock(&adc_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!sample_invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) iio_push_to_buffers_with_timestamp(indio_dev, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct iio_chan_spec const *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!adc_dev->shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cc10001_adc_power_up(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Calculate delay step for eoc and sampled data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cc10001_adc_start(adc_dev, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!adc_dev->shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cc10001_adc_power_down(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mutex_lock(&adc_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_unlock(&adc_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (*val == CC10001_INVALID_SAMPLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = regulator_get_voltage(adc_dev->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const unsigned long *scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) kfree(adc_dev->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!adc_dev->buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct iio_info cc10001_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .read_raw = &cc10001_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .update_scan_mode = &cc10001_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long channel_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct iio_chan_spec *chan_array, *timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int bit, idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) indio_dev->num_channels = bitmap_weight(&channel_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CC10001_ADC_NUM_CHANNELS) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sizeof(struct iio_chan_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!chan_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct iio_chan_spec *chan = &chan_array[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) chan->type = IIO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) chan->indexed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) chan->channel = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) chan->scan_index = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) chan->scan_type.sign = 'u';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) chan->scan_type.realbits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) chan->scan_type.storagebits = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) timestamp = &chan_array[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) timestamp->type = IIO_TIMESTAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) timestamp->channel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) timestamp->scan_index = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) timestamp->scan_type.sign = 's';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) timestamp->scan_type.realbits = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) timestamp->scan_type.storagebits = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) indio_dev->channels = chan_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int cc10001_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct cc10001_adc_device *adc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long adc_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned long channel_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) adc_dev->shared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) channel_map &= ~ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (IS_ERR(adc_dev->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return PTR_ERR(adc_dev->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = regulator_enable(adc_dev->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) indio_dev->info = &cc10001_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (IS_ERR(adc_dev->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = PTR_ERR(adc_dev->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (IS_ERR(adc_dev->adc_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(&pdev->dev, "failed to get the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = PTR_ERR(adc_dev->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = clk_prepare_enable(adc_dev->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(&pdev->dev, "failed to enable the clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto err_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!adc_clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(&pdev->dev, "null clock rate!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * There is only one register to power-up/power-down the AUX ADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * If the ADC is shared among multiple CPUs, always power it up here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * If the ADC is used only by the MIPS, power-up/power-down at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (adc_dev->shared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cc10001_adc_power_up(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Setup the ADC channels available on the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = cc10001_adc_channel_init(indio_dev, channel_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mutex_init(&adc_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) &cc10001_adc_trigger_h, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto err_cleanup_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err_cleanup_buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clk_disable_unprepare(adc_dev->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) err_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) regulator_disable(adc_dev->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int cc10001_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cc10001_adc_power_down(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk_disable_unprepare(adc_dev->adc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) regulator_disable(adc_dev->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct of_device_id cc10001_adc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .compatible = "cosmic,10001-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct platform_driver cc10001_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "cc10001-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .of_match_table = cc10001_adc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .probe = cc10001_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .remove = cc10001_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) module_platform_driver(cc10001_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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