^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Marvell Berlin2 ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Marvell Technology Group Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Antoine Tenart <antoine.tenart@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BERLIN2_SM_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BERLIN2_SM_CTRL_SM_SOC_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BERLIN2_SM_CTRL_SOC_SM_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BERLIN2_SM_CTRL_ADC_SEL(x) ((x) << 5) /* 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BERLIN2_SM_CTRL_ADC_SEL_MASK GENMASK(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BERLIN2_SM_CTRL_ADC_POWER BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV2 (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV3 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV4 (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV8 (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BERLIN2_SM_CTRL_ADC_CLKSEL_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BERLIN2_SM_CTRL_ADC_START BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BERLIN2_SM_CTRL_ADC_RESET BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BERLIN2_SM_CTRL_ADC_BANDGAP_RDY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BERLIN2_SM_CTRL_ADC_CONT_SINGLE (0x0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BERLIN2_SM_CTRL_ADC_CONT_CONTINUOUS (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BERLIN2_SM_CTRL_ADC_BUFFER_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BERLIN2_SM_CTRL_ADC_VREF_EXT (0x0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BERLIN2_SM_CTRL_ADC_VREF_INT (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BERLIN2_SM_CTRL_ADC_ROTATE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BERLIN2_SM_CTRL_TSEN_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_125 (0x0 << 21) /* 1.25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_250 (0x1 << 21) /* 2.5 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BERLIN2_SM_CTRL_TSEN_MODE_0_125 (0x0 << 22) /* 0-125 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BERLIN2_SM_CTRL_TSEN_MODE_10_50 (0x1 << 22) /* 10-50 C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BERLIN2_SM_CTRL_TSEN_RESET BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BERLIN2_SM_ADC_DATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BERLIN2_SM_ADC_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BERLIN2_SM_ADC_STATUS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BERLIN2_SM_ADC_STATUS_DATA_RDY(x) BIT(x) /* 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BERLIN2_SM_ADC_STATUS_INT_EN(x) (BIT(x) << 16) /* 0-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BERLIN2_SM_ADC_STATUS_INT_EN_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BERLIN2_SM_TSEN_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BERLIN2_SM_TSEN_STATUS_DATA_RDY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BERLIN2_SM_TSEN_STATUS_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BERLIN2_SM_TSEN_DATA 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BERLIN2_SM_TSEN_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BERLIN2_SM_TSEN_CTRL 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BERLIN2_SM_TSEN_CTRL_START BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BERLIN2_SM_TSEN_CTRL_SETTLING_4 (0x0 << 21) /* 4 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BERLIN2_SM_TSEN_CTRL_SETTLING_12 (0x1 << 21) /* 12 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BERLIN2_SM_TSEN_CTRL_SETTLING_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BERLIN2_SM_TSEN_CTRL_TRIM(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BERLIN2_SM_TSEN_CTRL_TRIM_MASK GENMASK(25, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct berlin2_adc_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool data_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BERLIN2_ADC_CHANNEL(n, t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .channel = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .datasheet_name = "channel"#n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .type = t, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct iio_chan_spec berlin2_adc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BERLIN2_ADC_CHANNEL(0, IIO_VOLTAGE), /* external input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) BERLIN2_ADC_CHANNEL(1, IIO_VOLTAGE), /* external input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) BERLIN2_ADC_CHANNEL(2, IIO_VOLTAGE), /* external input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BERLIN2_ADC_CHANNEL(3, IIO_VOLTAGE), /* external input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BERLIN2_ADC_CHANNEL(4, IIO_VOLTAGE), /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) BERLIN2_ADC_CHANNEL(5, IIO_VOLTAGE), /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { /* temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .channel = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .datasheet_name = "channel6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .indexed = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) BERLIN2_ADC_CHANNEL(7, IIO_VOLTAGE), /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IIO_CHAN_SOFT_TIMESTAMP(8), /* timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int berlin2_adc_read(struct iio_dev *indio_dev, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct berlin2_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int data, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Enable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) BERLIN2_SM_ADC_STATUS_INT_EN(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Configure the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) BERLIN2_SM_CTRL_ADC_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BERLIN2_SM_CTRL_ADC_SEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) BERLIN2_SM_CTRL_ADC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BERLIN2_SM_CTRL_ADC_SEL(channel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) BERLIN2_SM_CTRL_ADC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Disable the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) regmap_update_bits(priv->regmap, BERLIN2_SM_ADC_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) BERLIN2_SM_ADC_STATUS_INT_EN(channel), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BERLIN2_SM_CTRL_ADC_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) priv->data_available = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int berlin2_adc_tsen_read(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct berlin2_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int data, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) BERLIN2_SM_TSEN_STATUS_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Configure the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) BERLIN2_SM_CTRL_TSEN_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) BERLIN2_SM_CTRL_ADC_ROTATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BERLIN2_SM_CTRL_ADC_ROTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Configure the temperature sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) BERLIN2_SM_TSEN_CTRL_TRIM_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BERLIN2_SM_TSEN_CTRL_SETTLING_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) BERLIN2_SM_TSEN_CTRL_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BERLIN2_SM_TSEN_CTRL_TRIM(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) BERLIN2_SM_TSEN_CTRL_SETTLING_12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BERLIN2_SM_TSEN_CTRL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) BERLIN2_SM_TSEN_STATUS_INT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) BERLIN2_SM_TSEN_CTRL_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) priv->data_available = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int berlin2_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (chan->type != IIO_VOLTAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *val = berlin2_adc_read(indio_dev, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case IIO_CHAN_INFO_PROCESSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (chan->type != IIO_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) temp = berlin2_adc_tsen_read(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (temp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (temp > 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) temp -= 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Convert to milli Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *val = ((temp * 100000) / 264 - 270000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static irqreturn_t berlin2_adc_irq(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct berlin2_adc_priv *priv = iio_priv(private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) regmap_read(priv->regmap, BERLIN2_SM_ADC_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (val & BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_read(priv->regmap, BERLIN2_SM_ADC_DATA, &priv->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) priv->data &= BERLIN2_SM_ADC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) val &= ~BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) priv->data_available = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) wake_up_interruptible(&priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct berlin2_adc_priv *priv = iio_priv(private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_read(priv->regmap, BERLIN2_SM_TSEN_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (val & BERLIN2_SM_TSEN_STATUS_DATA_RDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) regmap_read(priv->regmap, BERLIN2_SM_TSEN_DATA, &priv->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) priv->data &= BERLIN2_SM_TSEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val &= ~BERLIN2_SM_TSEN_STATUS_DATA_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) priv->data_available = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) wake_up_interruptible(&priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct iio_info berlin2_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .read_raw = berlin2_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int berlin2_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct berlin2_adc_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct device_node *parent_np = of_get_parent(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int irq, tsen_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) priv->regmap = syscon_node_to_regmap(parent_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) of_node_put(parent_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(priv->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) irq = platform_get_irq_byname(pdev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) tsen_irq = platform_get_irq_byname(pdev, "tsen");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (tsen_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return tsen_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = devm_request_irq(&pdev->dev, irq, berlin2_adc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pdev->dev.driver->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = devm_request_irq(&pdev->dev, tsen_irq, berlin2_adc_tsen_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0, pdev->dev.driver->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) init_waitqueue_head(&priv->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) indio_dev->info = &berlin2_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) indio_dev->channels = berlin2_adc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) indio_dev->num_channels = ARRAY_SIZE(berlin2_adc_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Power up the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) BERLIN2_SM_CTRL_ADC_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) BERLIN2_SM_CTRL_ADC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Power down the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) BERLIN2_SM_CTRL_ADC_POWER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int berlin2_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct berlin2_adc_priv *priv = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Power down the ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) BERLIN2_SM_CTRL_ADC_POWER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct of_device_id berlin2_adc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .compatible = "marvell,berlin2-adc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_DEVICE_TABLE(of, berlin2_adc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct platform_driver berlin2_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "berlin2-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .of_match_table = berlin2_adc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .probe = berlin2_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .remove = berlin2_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) module_platform_driver(berlin2_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_DESCRIPTION("Marvell Berlin2 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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