^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* ADC driver for AXP20X and AXP22X PMICs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2016 Free Electrons NextThing Co.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Quentin Schulz <quentin.schulz@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/axp20x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AXP20X_ADC_EN1_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AXP22X_ADC_EN1_MASK (GENMASK(7, 5) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AXP20X_GPIO10_IN_RANGE_GPIO0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AXP20X_GPIO10_IN_RANGE_GPIO1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AXP20X_ADC_RATE_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AXP813_ADC_RATE_MASK (AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AXP20X_ADC_RATE_HZ(x) ((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AXP22X_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AXP813_TS_GPIO0_ADC_RATE_HZ(x) AXP20X_ADC_RATE_HZ(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AXP813_V_I_ADC_RATE_HZ(x) ((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AXP813_ADC_RATE_HZ(x) (AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .channel = _channel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .address = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .datasheet_name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .type = _type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .channel = _channel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .address = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) BIT(IIO_CHAN_INFO_SCALE) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) BIT(IIO_CHAN_INFO_OFFSET),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .datasheet_name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct axp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct axp20x_adc_iio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const struct axp_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum axp20x_adc_channel_v {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) AXP20X_ACIN_V = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) AXP20X_VBUS_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) AXP20X_TS_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) AXP20X_GPIO0_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AXP20X_GPIO1_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) AXP20X_IPSOUT_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) AXP20X_BATT_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum axp20x_adc_channel_i {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AXP20X_ACIN_I = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AXP20X_VBUS_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AXP20X_BATT_CHRG_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) AXP20X_BATT_DISCHRG_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum axp22x_adc_channel_v {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AXP22X_TS_IN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AXP22X_BATT_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum axp22x_adc_channel_i {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AXP22X_BATT_CHRG_I = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AXP22X_BATT_DISCHRG_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum axp813_adc_channel_v {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) AXP813_TS_IN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AXP813_GPIO0_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AXP813_BATT_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct iio_map axp20x_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .consumer_dev_name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .consumer_channel = "vbus_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .adc_channel_label = "vbus_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .consumer_dev_name = "axp20x-usb-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .consumer_channel = "vbus_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .adc_channel_label = "vbus_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .consumer_dev_name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .consumer_channel = "acin_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .adc_channel_label = "acin_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .consumer_dev_name = "axp20x-ac-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .consumer_channel = "acin_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .adc_channel_label = "acin_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .consumer_dev_name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .consumer_channel = "batt_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .adc_channel_label = "batt_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .consumer_dev_name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .consumer_channel = "batt_chrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .adc_channel_label = "batt_chrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .consumer_dev_name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .consumer_channel = "batt_dischrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .adc_channel_label = "batt_dischrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }, { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct iio_map axp22x_maps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .consumer_dev_name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .consumer_channel = "batt_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .adc_channel_label = "batt_v",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .consumer_dev_name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .consumer_channel = "batt_chrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .adc_channel_label = "batt_chrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .consumer_dev_name = "axp20x-battery-power-supply",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .consumer_channel = "batt_dischrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .adc_channel_label = "batt_dischrg_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }, { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Channels are mapped by physical system. Their channels share the same index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * i.e. acin_i is in_current0_raw and acin_v is in_voltage0_raw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * The only exception is for the battery. batt_v will be in_voltage6_raw and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * charge current in_current6_raw and discharge current will be in_current7_raw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct iio_chan_spec axp20x_adc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) AXP20X_ACIN_V_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) AXP20X_ADC_CHANNEL(AXP20X_ACIN_I, "acin_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) AXP20X_ACIN_I_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) AXP20X_ADC_CHANNEL(AXP20X_VBUS_V, "vbus_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) AXP20X_VBUS_V_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) AXP20X_ADC_CHANNEL(AXP20X_VBUS_I, "vbus_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) AXP20X_VBUS_I_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .address = AXP20X_TEMP_ADC_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .datasheet_name = "pmic_temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) AXP20X_GPIO0_V_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) AXP20X_GPIO1_V_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) AXP20X_ADC_CHANNEL(AXP20X_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) AXP20X_IPSOUT_V_HIGH_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) AXP20X_ADC_CHANNEL(AXP20X_BATT_V, "batt_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) AXP20X_BATT_V_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) AXP20X_ADC_CHANNEL(AXP20X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) AXP20X_BATT_CHRG_I_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) AXP20X_ADC_CHANNEL(AXP20X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) AXP20X_BATT_DISCHRG_I_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct iio_chan_spec axp22x_adc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .address = AXP22X_PMIC_TEMP_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .datasheet_name = "pmic_temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) AXP20X_ADC_CHANNEL(AXP22X_BATT_V, "batt_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) AXP20X_BATT_V_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) AXP20X_BATT_CHRG_I_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) AXP20X_BATT_DISCHRG_I_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct iio_chan_spec axp813_adc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .address = AXP22X_PMIC_TEMP_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .datasheet_name = "pmic_temp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AXP20X_ADC_CHANNEL(AXP813_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) AXP288_GP_ADC_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) AXP20X_ADC_CHANNEL(AXP813_BATT_V, "batt_v", IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) AXP20X_BATT_V_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) AXP20X_BATT_CHRG_I_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AXP20X_BATT_DISCHRG_I_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int axp20x_adc_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct axp20x_adc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int size = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * N.B.: Unlike the Chinese datasheets tell, the charging current is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * stored on 12 bits, not 13 bits. Only discharging current is on 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (chan->type == IIO_CURRENT && chan->channel == AXP20X_BATT_DISCHRG_I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) size = 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) size = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *val = axp20x_read_variable_width(info->regmap, chan->address, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int axp22x_adc_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct axp20x_adc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *val = axp20x_read_variable_width(info->regmap, chan->address, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int axp813_adc_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct axp20x_adc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *val = axp20x_read_variable_width(info->regmap, chan->address, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case AXP20X_ACIN_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case AXP20X_VBUS_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *val2 = 700000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case AXP20X_GPIO0_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case AXP20X_GPIO1_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *val2 = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case AXP20X_BATT_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *val2 = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case AXP20X_IPSOUT_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *val2 = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int axp813_adc_scale_voltage(int channel, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case AXP813_GPIO0_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *val2 = 800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case AXP813_BATT_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *val2 = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int axp20x_adc_scale_current(int channel, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case AXP20X_ACIN_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *val2 = 625000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case AXP20X_VBUS_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *val2 = 375000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case AXP20X_BATT_DISCHRG_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case AXP20X_BATT_CHRG_I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *val2 = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return axp20x_adc_scale_voltage(chan->channel, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return axp20x_adc_scale_current(chan->channel, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *val = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (chan->channel != AXP22X_BATT_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *val2 = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *val = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return axp813_adc_scale_voltage(chan->channel, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case IIO_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *val = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct axp20x_adc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch (channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case AXP20X_GPIO0_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) *val &= AXP20X_GPIO10_IN_RANGE_GPIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case AXP20X_GPIO1_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *val &= AXP20X_GPIO10_IN_RANGE_GPIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *val = *val ? 700000 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int axp20x_adc_offset(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return axp20x_adc_offset_voltage(indio_dev, chan->channel, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *val = -1447;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int axp20x_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return axp20x_adc_offset(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return axp20x_adc_scale(chan, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return axp20x_adc_raw(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int axp22x_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *val = -2677;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return axp22x_adc_scale(chan, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return axp22x_adc_raw(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int axp813_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *val = -2667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return axp813_adc_scale(chan, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return axp813_adc_raw(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int axp20x_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct iio_chan_spec const *chan, int val, int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct axp20x_adc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int reg, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * The AXP20X PMIC allows the user to choose between 0V and 0.7V offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * for (independently) GPIO0 and GPIO1 when in ADC mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (mask != IIO_CHAN_INFO_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (val != 0 && val != 700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val = val ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) switch (chan->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case AXP20X_GPIO0_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) reg = AXP20X_GPIO10_IN_RANGE_GPIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) regval = AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case AXP20X_GPIO1_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) reg = AXP20X_GPIO10_IN_RANGE_GPIO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) regval = AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct iio_info axp20x_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .read_raw = axp20x_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .write_raw = axp20x_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct iio_info axp22x_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .read_raw = axp22x_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct iio_info axp813_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .read_raw = axp813_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int axp20x_adc_rate(struct axp20x_adc_iio *info, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) AXP20X_ADC_RATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) AXP20X_ADC_RATE_HZ(rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int axp22x_adc_rate(struct axp20x_adc_iio *info, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) AXP20X_ADC_RATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) AXP22X_ADC_RATE_HZ(rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return regmap_update_bits(info->regmap, AXP813_ADC_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) AXP813_ADC_RATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) AXP813_ADC_RATE_HZ(rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct axp_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) const struct iio_info *iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct iio_chan_spec const *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned long adc_en1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int (*adc_rate)(struct axp20x_adc_iio *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bool adc_en2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct iio_map *maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct axp_data axp20x_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .iio_info = &axp20x_adc_iio_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .num_channels = ARRAY_SIZE(axp20x_adc_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .channels = axp20x_adc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .adc_en1_mask = AXP20X_ADC_EN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .adc_rate = axp20x_adc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .adc_en2 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .maps = axp20x_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const struct axp_data axp22x_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .iio_info = &axp22x_adc_iio_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .num_channels = ARRAY_SIZE(axp22x_adc_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .channels = axp22x_adc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .adc_en1_mask = AXP22X_ADC_EN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .adc_rate = axp22x_adc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .adc_en2 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .maps = axp22x_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct axp_data axp813_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .iio_info = &axp813_adc_iio_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .num_channels = ARRAY_SIZE(axp813_adc_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .channels = axp813_adc_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .adc_en1_mask = AXP22X_ADC_EN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .adc_rate = axp813_adc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .adc_en2 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .maps = axp22x_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct of_device_id axp20x_adc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { .compatible = "x-powers,axp209-adc", .data = (void *)&axp20x_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { .compatible = "x-powers,axp221-adc", .data = (void *)&axp22x_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { .compatible = "x-powers,axp813-adc", .data = (void *)&axp813_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_DEVICE_TABLE(of, axp20x_adc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const struct platform_device_id axp20x_adc_id_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { .name = "axp813-adc", .driver_data = (kernel_ulong_t)&axp813_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MODULE_DEVICE_TABLE(platform, axp20x_adc_id_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int axp20x_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct axp20x_adc_iio *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct axp20x_dev *axp20x_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) axp20x_dev = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) info->regmap = axp20x_dev->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!dev_fwnode(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) const struct platform_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) id = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) info->data = (const struct axp_data *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) info->data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) indio_dev->name = platform_get_device_id(pdev)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) indio_dev->info = info->data->iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) indio_dev->num_channels = info->data->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) indio_dev->channels = info->data->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Enable the ADCs on IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) regmap_write(info->regmap, AXP20X_ADC_EN1, info->data->adc_en1_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (info->data->adc_en2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Enable GPIO0/1 and internal temperature ADCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) regmap_update_bits(info->regmap, AXP20X_ADC_EN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) AXP20X_ADC_EN2_MASK, AXP20X_ADC_EN2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Configure ADCs rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) info->data->adc_rate(info, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = iio_map_array_register(indio_dev, info->data->maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_err(&pdev->dev, "failed to register IIO maps: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto fail_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(&pdev->dev, "could not register the device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto fail_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) fail_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) iio_map_array_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) fail_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (info->data->adc_en2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int axp20x_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct axp20x_adc_iio *info = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) iio_map_array_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) regmap_write(info->regmap, AXP20X_ADC_EN1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (info->data->adc_en2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) regmap_write(info->regmap, AXP20X_ADC_EN2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct platform_driver axp20x_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .name = "axp20x-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .of_match_table = axp20x_adc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .id_table = axp20x_adc_id_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .probe = axp20x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .remove = axp20x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) module_platform_driver(axp20x_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MODULE_DESCRIPTION("ADC driver for AXP20X and AXP22X PMICs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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