^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atmel ADC driver for SAMA5D2 devices and compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Atmel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_SAMA5D2_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AT91_SAMA5D2_CR_SWRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Start Conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AT91_SAMA5D2_CR_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Touchscreen Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Comparison Restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_SAMA5D2_CR_CMPRST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AT91_SAMA5D2_MR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Trigger Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* ADTRG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* TIOA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* TIOA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* TIOA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* PWM event line 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PWM event line 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* TIOA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* RTCOUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Sleep Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AT91_SAMA5D2_MR_SLEEP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Fast Wake Up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AT91_SAMA5D2_MR_FWUP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Prescaler Rate Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Startup Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Analog Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AT91_SAMA5D2_MR_ANACH BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Tracking Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Transfer Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Use Sequence Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AT91_SAMA5D2_MR_USEQ BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Channel Sequence Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AT91_SAMA5D2_SEQR1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Channel Sequence Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AT91_SAMA5D2_SEQR2 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Channel Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AT91_SAMA5D2_CHER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Channel Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AT91_SAMA5D2_CHDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Channel Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AT91_SAMA5D2_CHSR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Last Converted Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AT91_SAMA5D2_LCDR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AT91_SAMA5D2_IER 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Interrupt Enable Register - TS X measurement ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AT91_SAMA5D2_IER_XRDY BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Interrupt Enable Register - TS Y measurement ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AT91_SAMA5D2_IER_YRDY BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Interrupt Enable Register - TS pressure measurement ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AT91_SAMA5D2_IER_PRDY BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Interrupt Enable Register - Data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AT91_SAMA5D2_IER_DRDY BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Interrupt Enable Register - general overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AT91_SAMA5D2_IER_GOVRE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Interrupt Enable Register - Pen detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AT91_SAMA5D2_IER_PEN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Interrupt Enable Register - No pen detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AT91_SAMA5D2_IER_NOPEN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Interrupt Disable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AT91_SAMA5D2_IDR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AT91_SAMA5D2_IMR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AT91_SAMA5D2_ISR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Interrupt Status Register - Pen touching sense status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AT91_SAMA5D2_ISR_PENS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Last Channel Trigger Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AT91_SAMA5D2_LCTMR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Last Channel Compare Window Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AT91_SAMA5D2_LCCWR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Overrun Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AT91_SAMA5D2_OVER 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Extended Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AT91_SAMA5D2_EMR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Extended Mode Register - Oversampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Extended Mode Register - Averaging on single trigger event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Compare Window Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AT91_SAMA5D2_CWR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Channel Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AT91_SAMA5D2_CGR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Channel Offset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AT91_SAMA5D2_COR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Channel Data Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AT91_SAMA5D2_CDR0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Analog Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AT91_SAMA5D2_ACR 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Analog Control Register - Pen detect sensitivity mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Touchscreen Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AT91_SAMA5D2_TSMR 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Touchscreen Mode Register - No touch mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Touchscreen Mode Register - 5 wire screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Touchscreen Mode Register - Average samples mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Touchscreen Mode Register - Average samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Touchscreen Mode Register - Touch/trigger frequency ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Touchscreen Mode Register - Pen Debounce Time mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Touchscreen Mode Register - Pen Debounce Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Touchscreen Mode Register - No DMA for touch measurements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Touchscreen Mode Register - Disable pen detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Touchscreen Mode Register - Enable pen detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Touchscreen X Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AT91_SAMA5D2_XPOSR 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Touchscreen Y Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AT91_SAMA5D2_YPOSR 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Touchscreen Pressure Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AT91_SAMA5D2_PRESSR 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Trigger Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AT91_SAMA5D2_TRGR 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Mask for TRGMOD field of TRGR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* No trigger, only software trigger can start conversions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Trigger Mode external trigger rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Trigger Mode external trigger falling edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Trigger Mode external trigger any edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Trigger Mode internal periodic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Trigger Mode - trigger period mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Trigger Mode - trigger period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Correction Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AT91_SAMA5D2_COSR 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Correction Value Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AT91_SAMA5D2_CVR 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Channel Error Correction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AT91_SAMA5D2_CECR 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Write Protection Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AT91_SAMA5D2_WPMR 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Write Protection Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AT91_SAMA5D2_WPSR 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AT91_SAMA5D2_VERSION 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AT91_SAMA5D2_HW_TRIG_CNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AT91_SAMA5D2_MAX_POS_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Maximum number of bytes to hold conversion from all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * without the timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* This total must also include the timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AT91_HWFIFO_MAX_SIZE_STR "128"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AT91_HWFIFO_MAX_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Possible values for oversampling ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AT91_OSR_1SAMPLES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AT91_OSR_4SAMPLES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AT91_OSR_16SAMPLES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .channel = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .address = addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .scan_index = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .realbits = 14, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .datasheet_name = "CH"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .differential = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .channel = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .channel2 = num2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .address = addr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .realbits = 14, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .datasheet_name = "CH"#num"-CH"#num2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .type = IIO_POSITIONRELATIVE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .channel = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .channel2 = mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .scan_index = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .datasheet_name = name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .type = IIO_PRESSURE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .channel = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .scan_index = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .datasheet_name = name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct at91_adc_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned startup_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned min_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned max_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct at91_adc_trigger {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int trgmod_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int edge_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bool hw_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * struct at91_adc_dma - at91-sama5d2 dma information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @dma_chan: the dma channel acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @rx_buf: dma coherent allocated area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @rx_dma_buf: dma handler for the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @phys_addr: physical address of the ADC base register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @buf_idx: index inside the dma buffer where reading was last done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @rx_buf_sz: size of buffer used by DMA operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @watermark: number of conversions to copy before DMA triggers irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @dma_ts: hold the start timestamp of dma operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct at91_adc_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dma_addr_t rx_dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) phys_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int rx_buf_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) s64 dma_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @sample_period_val: the value for periodic trigger interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @touching: is the pen touching the screen or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @x_pos: temporary placeholder for pressure computation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @channels_bitmask: bitmask with the touchscreen channels enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * @workq: workqueue for buffer data pushing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct at91_adc_touch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u16 sample_period_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bool touching;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u16 x_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned long channels_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct work_struct workq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct at91_adc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct clk *per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int current_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct at91_adc_trigger *selected_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) const struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bool conversion_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 conversion_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int oversampling_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct at91_adc_soc_info soc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) wait_queue_head_t wq_data_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct at91_adc_dma dma_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct at91_adc_touch touch_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Ensure naturally aligned timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * lock to prevent concurrent 'single conversion' requests through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const struct at91_adc_trigger at91_adc_trigger_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "external_rising",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .edge_type = IRQ_TYPE_EDGE_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .hw_trig = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "external_falling",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .edge_type = IRQ_TYPE_EDGE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .hw_trig = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "external_any",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .edge_type = IRQ_TYPE_EDGE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .hw_trig = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "software",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .edge_type = IRQ_TYPE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .hw_trig = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct iio_chan_spec at91_adc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (i = 0; i < indio_dev->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (indio_dev->channels[i].scan_index == chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline struct iio_chan_spec const *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int index = at91_adc_chan_xlate(indio_dev, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return indio_dev->channels + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const struct of_phandle_args *iiospec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct iio_chan_spec const *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) at91_adc_chan_get(indio_dev, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mask |= BIT(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return mask & GENMASK(11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void at91_adc_config_emr(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* configure the extended mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* select oversampling per single trigger event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) emr |= AT91_SAMA5D2_EMR_ASTE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* delete leftover content if it's the case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* select oversampling ratio from configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) switch (st->oversampling_ratio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case AT91_OSR_1SAMPLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) AT91_SAMA5D2_EMR_OSR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case AT91_OSR_4SAMPLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) AT91_SAMA5D2_EMR_OSR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case AT91_OSR_16SAMPLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) AT91_SAMA5D2_EMR_OSR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * in this case we only have 12 bits of real data, but channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * is registered as 14 bits, so shift left two bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) *val <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * in this case we have 13 bits of real data, but channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * is registered as 14 bits, so left shift one bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *val <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int i = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u16 *buf_u16 = (u16 *) buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * We are converting each two bytes (each sample).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * First convert the byte based array to u16, and convert each sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * Each value is two bytes in an array of chars, so to not shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * more than we need, save the value separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * len is in bytes, so divide by two to get number of samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) while (i < len / 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) val = buf_u16[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) at91_adc_adjust_val_osr(st, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) buf_u16[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 clk_khz = st->current_sample_rate / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u16 pendbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 tsmr, acr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* disabling touch IRQs and setting mode to no touch enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) at91_adc_writel(st, AT91_SAMA5D2_IDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * debounce time is in microseconds, we need it in milliseconds to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * multiply with kilohertz, so, divide by 1000, but after the multiply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * round up to make sure pendbc is at least 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) clk_khz / 1000, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* get the required exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) while (pendbc >> i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pendbc = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) AT91_SAMA5D2_TSMR_PENDBC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Sample Period Time = (TRGPER + 1) / ADCClock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) st->touch_st.sample_period_val =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) clk_khz / 1000) - 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* enable pen detect IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 scale, result, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * to obtain the actual position we must divide by scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * and multiply with max, where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* first half of register is the x or y, second half is the scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) val = at91_adc_readl(st, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_dbg(&st->indio_dev->dev, "pos is 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pos = val & AT91_SAMA5D2_XYZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (scale == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_err(&st->indio_dev->dev, "scale is 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) result /= scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return st->touch_st.x_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 z1, z2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 rxp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 factor = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* calculate the pressure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) z1 = val & AT91_SAMA5D2_XYZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (z1 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pres = rxp * (st->touch_st.x_pos * factor / 1024) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) (z2 * factor / z1 - factor) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pres = 0xFFFF; /* no pen contact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * We compute it this way, but let's return it in the expected way,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * growing from 0 to 0xFFFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0xFFFF - pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!st->touch_st.touching)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *val = at91_adc_touch_x_pos(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *val = at91_adc_touch_y_pos(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (!st->touch_st.touching)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) *val = at91_adc_touch_pressure(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct iio_dev *indio = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct at91_adc_state *st = iio_priv(indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* clear TRGMOD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) status |= st->selected_trig->trgmod_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* set/unset hw trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int at91_adc_reenable_trigger(struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct iio_dev *indio = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct at91_adc_state *st = iio_priv(indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* if we are using DMA, we must not reenable irq after each trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) enable_irq(st->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Needed to ACK the DRDY interruption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) at91_adc_readl(st, AT91_SAMA5D2_LCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const struct iio_trigger_ops at91_adc_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .set_trigger_state = &at91_adc_configure_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .try_reenable = &at91_adc_reenable_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .validate_device = iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int at91_adc_dma_size_done(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int i, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) status = dmaengine_tx_status(st->dma_st.dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) st->dma_st.dma_chan->cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (status != DMA_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* Transferred length is size in bytes from end of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) i = st->dma_st.rx_buf_sz - state.residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Return available bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (i >= st->dma_st.buf_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) size = i - st->dma_st.buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void at91_dma_buffer_done(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct iio_dev *indio_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) iio_trigger_poll_chained(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int at91_adc_dma_start(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* we start a new DMA, so set buffer index to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) st->dma_st.buf_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * compute buffer size w.r.t. watermark and enabled channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * scan_bytes is aligned so we need an exact size for DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) st->dma_st.rx_buf_sz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct iio_chan_spec const *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) at91_adc_chan_get(indio_dev, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) st->dma_st.rx_buf_sz *= st->dma_st.watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Prepare a DMA cyclic transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) st->dma_st.rx_dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) st->dma_st.rx_buf_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) st->dma_st.rx_buf_sz / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) desc->callback = at91_dma_buffer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) desc->callback_param = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) cookie = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = dma_submit_error(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dmaengine_terminate_async(st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* enable general overrun error signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Issue pending DMA requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dma_async_issue_pending(st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* consider current time as DMA start time for timestamps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* if using DMA, we do not use our own IRQ (we use DMA-controller) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* if the trigger is not ours, then it has its own IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (iio_trigger_validate_own_device(indio->trig, indio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return !!bitmap_subset(indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) &st->touch_st.channels_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) AT91_SAMA5D2_MAX_CHAN_IDX + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* check if we are enabling triggered buffer or the touchscreen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (at91_adc_current_chan_is_touch(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return at91_adc_configure_touch(st, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* if we are not in triggered mode, we cannot enable the buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* we continue with the triggered buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = at91_adc_dma_start(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_err(&indio_dev->dev, "buffer prepare failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct iio_chan_spec const *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) at91_adc_chan_get(indio_dev, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 cor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* these channel types cannot be handled by this trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (chan->type == IIO_POSITIONRELATIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) chan->type == IIO_PRESSURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (chan->differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) cor |= (BIT(chan->channel) | BIT(chan->channel2)) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) AT91_SAMA5D2_COR_DIFF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) cor &= ~(BIT(chan->channel) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) AT91_SAMA5D2_COR_DIFF_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (at91_adc_buffer_check_use_irq(indio_dev, st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* check if we are disabling triggered buffer or the touchscreen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (at91_adc_current_chan_is_touch(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return at91_adc_configure_touch(st, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* if we are not in triggered mode, nothing to do here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * For each enable channel we must disable it in hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * In the case of DMA, we must read the last converted value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * to clear EOC status and not get a possible interrupt later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * This value is being read by DMA from LCDR anyway, so it's not lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct iio_chan_spec const *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) at91_adc_chan_get(indio_dev, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* these channel types are virtual, no need to do anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (chan->type == IIO_POSITIONRELATIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) chan->type == IIO_PRESSURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) at91_adc_readl(st, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (at91_adc_buffer_check_use_irq(indio_dev, st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* read overflow register to clear possible overflow status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) at91_adc_readl(st, AT91_SAMA5D2_OVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* if we are using DMA we must clear registers and end DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dmaengine_terminate_sync(st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .postdisable = &at91_adc_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) char *trigger_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) indio->id, trigger_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) trig->dev.parent = indio->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) iio_trigger_set_drvdata(trig, indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) trig->ops = &at91_adc_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = devm_iio_trigger_register(&indio->dev, trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int at91_adc_trigger_init(struct iio_dev *indio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct at91_adc_state *st = iio_priv(indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (IS_ERR(st->trig)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_err(&indio->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "could not allocate trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return PTR_ERR(st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct iio_poll_func *pf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned int timeout = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Check if the conversion is ready. If not, wait a little bit, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * in case of timeout exit with an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) usleep_range(50, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Cannot read data, not ready. Continue without reporting data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct iio_chan_spec const *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) at91_adc_chan_get(indio_dev, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * Our external trigger only supports the voltage channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * In case someone requested a different type of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * just put zeroes to buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * This should not happen because we check the scan mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * and scan mask when we enable the buffer, and we don't allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * the buffer to start with a mixed mask (voltage and something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * else).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * Thus, emit a warning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (chan->type == IIO_VOLTAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) val = at91_adc_readl(st, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) at91_adc_adjust_val_osr(st, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) st->buffer[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) st->buffer[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) WARN(true, "This trigger cannot handle this type of channel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int transferred_len = at91_adc_dma_size_done(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) s64 ns = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) s64 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int sample_index = 0, sample_count, sample_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* if we reached this point, we cannot sample faster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (status & AT91_SAMA5D2_IER_GOVRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) pr_info_ratelimited("%s: conversion overrun detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) indio_dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) sample_count = div_s64(transferred_len, sample_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * interval between samples is total time since last transfer handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * divided by the number of samples (total size divided by sample size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) while (transferred_len >= sample_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * for all the values in the current sample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * adjust the values inside the buffer for oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) at91_adc_adjust_val_osr_array(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) &st->dma_st.rx_buf[st->dma_st.buf_idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) sample_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) iio_push_to_buffers_with_timestamp(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) (st->dma_st.rx_buf + st->dma_st.buf_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) (st->dma_st.dma_ts + interval * sample_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* adjust remaining length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) transferred_len -= sample_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* adjust buffer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) st->dma_st.buf_idx += sample_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* in case of reaching end of buffer, reset index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) st->dma_st.buf_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) sample_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* adjust saved time for next transfer handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * If it's not our trigger, start a conversion now, as we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * actually polling the trigger now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) at91_adc_trigger_handler_dma(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) at91_adc_trigger_handler_nodma(indio_dev, pf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int at91_adc_buffer_init(struct iio_dev *indio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return devm_iio_triggered_buffer_setup(&indio->dev, indio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) &at91_adc_trigger_handler, &at91_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static unsigned at91_adc_startup_time(unsigned startup_time_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) unsigned adc_clk_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const unsigned int startup_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) 0, 8, 16, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) 64, 80, 96, 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) 512, 576, 640, 704,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) 768, 832, 896, 960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) unsigned ticks_min, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * Since the adc frequency is checked before, there is no reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * to not meet the startup time constraint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ticks_min = startup_time_min * adc_clk_khz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (startup_lookup[i] > ticks_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) unsigned f_per, prescal, startup, mr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) f_per = clk_get_rate(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) prescal = (f_per / (2 * freq)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) startup = at91_adc_startup_time(st->soc_info.startup_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) freq / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) mr |= AT91_SAMA5D2_MR_STARTUP(startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) freq, startup, prescal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) st->current_sample_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return st->current_sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct iio_chan_spec const *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) at91_adc_chan_get(indio_dev, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (chan->type == IIO_POSITIONRELATIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) at91_adc_read_position(st, chan->channel, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) else if (chan->type == IIO_PRESSURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) at91_adc_read_pressure(st, chan->channel, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) st->buffer[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * Schedule work to push to buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * This is intended to push to the callback buffer that another driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * registered. We are still in a handler from our IRQ. If we push
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * directly, it means the other driver has it's callback called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * from our IRQ context. Which is something we better avoid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * Let's schedule it after our IRQ is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) schedule_work(&st->touch_st.workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) AT91_SAMA5D2_IER_PRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) at91_adc_writel(st, AT91_SAMA5D2_TRGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) st->touch_st.touching = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) at91_adc_writel(st, AT91_SAMA5D2_TRGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) AT91_SAMA5D2_IER_PRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) st->touch_st.touching = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) at91_adc_touch_data_handler(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static void at91_adc_workq_handler(struct work_struct *workq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct at91_adc_touch *touch_st = container_of(workq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct at91_adc_touch, workq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct at91_adc_state *st = container_of(touch_st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct at91_adc_state, touch_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct iio_dev *indio_dev = st->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) iio_push_to_buffers(indio_dev, st->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static irqreturn_t at91_adc_interrupt(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct iio_dev *indio = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct at91_adc_state *st = iio_priv(indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) AT91_SAMA5D2_IER_PRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!(status & imr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (status & AT91_SAMA5D2_IER_PEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* pen detected IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) at91_adc_pen_detect_interrupt(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* nopen detected IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) at91_adc_no_pen_detect_interrupt(indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ((status & rdy_mask) == rdy_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* periodic trigger IRQ - during pen sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) at91_adc_touch_data_handler(indio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) } else if (status & AT91_SAMA5D2_ISR_PENS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * touching, but the measurements are not ready yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * read and ignore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else if (iio_buffer_enabled(indio) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) (status & AT91_SAMA5D2_IER_DRDY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* triggered buffer without DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) iio_trigger_poll(indio->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* triggered buffer with DMA - should not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) WARN(true, "Unexpected irq occurred\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) } else if (!iio_buffer_enabled(indio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* software requested conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) st->conversion_value = at91_adc_readl(st, st->chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) st->conversion_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) wake_up_interruptible(&st->wq_data_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct iio_chan_spec const *chan, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u32 cor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u16 tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * Keep in mind that we cannot use software trigger or touchscreen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * if external trigger is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (chan->type == IIO_POSITIONRELATIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ret = at91_adc_read_position(st, chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) &tmp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) *val = tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return at91_adc_adjust_val_osr(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (chan->type == IIO_PRESSURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ret = at91_adc_read_pressure(st, chan->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) &tmp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) *val = tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return at91_adc_adjust_val_osr(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* in this case we have a voltage channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) st->chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (chan->differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) AT91_SAMA5D2_COR_DIFF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = wait_event_interruptible_timeout(st->wq_data_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) st->conversion_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (ret > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) *val = st->conversion_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ret = at91_adc_adjust_val_osr(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (chan->scan_type.sign == 's')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) *val = sign_extend32(*val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) chan->scan_type.realbits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) st->conversion_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Needed to ACK the DRDY interruption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) at91_adc_readl(st, AT91_SAMA5D2_LCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static int at91_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return at91_adc_read_info_raw(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) *val = st->vref_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (chan->differential)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) *val *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) *val = at91_adc_get_sample_freq(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *val = st->oversampling_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static int at91_adc_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) (val != AT91_OSR_16SAMPLES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* if no change, optimize out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (val == st->oversampling_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) st->oversampling_ratio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* update ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) at91_adc_config_emr(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (val < st->soc_info.min_sample_rate ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) val > st->soc_info.max_sample_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) at91_adc_setup_samp_freq(indio_dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static void at91_adc_dma_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct dma_slave_config config = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * We make the buffer double the size of the fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * such that DMA uses one half of the buffer (full fifo size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * and the software uses the other half to read/write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (IS_ERR(st->dma_st.dma_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev_info(&pdev->dev, "can't get DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) st->dma_st.dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) goto dma_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pages * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) &st->dma_st.rx_dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (!st->dma_st.rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) goto dma_chan_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* Configure DMA channel to read data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) config.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) + AT91_SAMA5D2_LCDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) config.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) config.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dev_info(&pdev->dev, "can't configure DMA slave\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) goto dma_free_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) dma_chan_name(st->dma_st.dma_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dma_free_area:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dma_chan_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dma_release_channel(st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) st->dma_st.dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dma_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_info(&pdev->dev, "continuing without DMA support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static void at91_adc_dma_disable(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* if we are not using DMA, just return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (!st->dma_st.dma_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* wait for all transactions to be terminated first*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dmaengine_terminate_sync(st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) dma_release_channel(st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) st->dma_st.dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_info(&pdev->dev, "continuing without DMA support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (val > AT91_HWFIFO_MAX_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (!st->selected_trig->hw_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) st->dma_st.watermark = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * The logic here is: if we have watermark 1, it means we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * each conversion with it's own IRQ, thus we don't need DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * If the watermark is higher, we do DMA to do all the transfers in bulk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (val == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) else if (val > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) at91_adc_dma_init(to_platform_device(&indio_dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * We can start the DMA only after setting the watermark and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * having the DMA initialization completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ret = at91_adc_buffer_prepare(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) const unsigned long *scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) AT91_SAMA5D2_MAX_CHAN_IDX + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * if the new bitmap is a combination of touchscreen and regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * channels, then we are not fine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) AT91_SAMA5D2_MAX_CHAN_IDX + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static void at91_adc_hw_init(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * Transfer field must be set to 2 according to the datasheet and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * allows different analog settings for each channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) at91_adc_writel(st, AT91_SAMA5D2_MR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* configure extended mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) at91_adc_config_emr(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static ssize_t at91_adc_get_fifo_state(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static ssize_t at91_adc_get_watermark(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) at91_adc_get_fifo_state, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) at91_adc_get_watermark, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static IIO_CONST_ATTR(oversampling_ratio_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) __stringify(AT91_OSR_1SAMPLES) " "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) __stringify(AT91_OSR_4SAMPLES) " "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) __stringify(AT91_OSR_16SAMPLES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static struct attribute *at91_adc_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const struct attribute_group at91_adc_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .attrs = at91_adc_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static const struct attribute *at91_adc_fifo_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static const struct iio_info at91_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .attrs = &at91_adc_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .read_raw = &at91_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .write_raw = &at91_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .update_scan_mode = &at91_adc_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .of_xlate = &at91_adc_of_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .hwfifo_set_watermark = &at91_adc_set_watermark,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static int at91_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct at91_adc_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 edge_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) indio_dev->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) indio_dev->info = &at91_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) indio_dev->channels = at91_adc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) st->indio_dev = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) bitmap_set(&st->touch_st.channels_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) bitmap_set(&st->touch_st.channels_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) bitmap_set(&st->touch_st.channels_bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) st->oversampling_ratio = AT91_OSR_1SAMPLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) "atmel,min-sample-rate-hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) &st->soc_info.min_sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) "invalid or missing value for atmel,min-sample-rate-hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) "atmel,max-sample-rate-hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) &st->soc_info.max_sample_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) "invalid or missing value for atmel,max-sample-rate-hz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) &st->soc_info.startup_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) "invalid or missing value for atmel,startup-time-ms\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) "atmel,trigger-edge-type", &edge_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dev_dbg(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) "atmel,trigger-edge-type not specified, only software trigger available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) st->selected_trig = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* find the right trigger, or no trigger at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (at91_adc_trigger_list[i].edge_type == edge_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) st->selected_trig = &at91_adc_trigger_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (!st->selected_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev_err(&pdev->dev, "invalid external trigger edge value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) init_waitqueue_head(&st->wq_data_available);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (IS_ERR(st->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return PTR_ERR(st->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* if we plan to use DMA, we need the physical address of the regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) st->dma_st.phys_addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) st->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (st->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (!st->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) st->irq = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return st->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (IS_ERR(st->per_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return PTR_ERR(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) st->reg = devm_regulator_get(&pdev->dev, "vddana");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) st->vref = devm_regulator_get(&pdev->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (IS_ERR(st->vref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return PTR_ERR(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) pdev->dev.driver->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret = regulator_enable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) goto reg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) st->vref_uv = regulator_get_voltage(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (st->vref_uv <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) goto vref_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) at91_adc_hw_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ret = clk_prepare_enable(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) goto vref_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = at91_adc_buffer_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) goto per_clk_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (st->selected_trig->hw_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret = at91_adc_trigger_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) dev_err(&pdev->dev, "couldn't setup the triggers.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) goto per_clk_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * Initially the iio buffer has a length of 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * a watermark of 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) st->dma_st.watermark = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) iio_buffer_set_attrs(indio_dev->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) at91_adc_fifo_attributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) goto dma_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (st->selected_trig->hw_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dev_info(&pdev->dev, "setting up trigger as %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) st->selected_trig->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dev_info(&pdev->dev, "version: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) dma_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) at91_adc_dma_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) per_clk_disable_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) clk_disable_unprepare(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) vref_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) reg_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static int at91_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) at91_adc_dma_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) clk_disable_unprepare(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static __maybe_unused int at91_adc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * Do a sofware reset of the ADC before we go to suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * this will ensure that all pins are free from being muxed by the ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * and can be used by for other devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * Otherwise, ADC will hog them and we can't go to suspend mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) clk_disable_unprepare(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static __maybe_unused int at91_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct at91_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) goto resume_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) goto resume_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ret = regulator_enable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) goto reg_disable_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ret = clk_prepare_enable(st->per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) goto vref_disable_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) at91_adc_hw_init(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* reconfiguring trigger hardware state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (!iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /* check if we are enabling triggered buffer or the touchscreen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (at91_adc_current_chan_is_touch(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) return at91_adc_configure_touch(st, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) return at91_adc_configure_trigger(st->trig, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* not needed but more explicit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) vref_disable_resume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) reg_disable_resume:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) resume_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) dev_err(&indio_dev->dev, "failed to resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const struct of_device_id at91_adc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .compatible = "atmel,sama5d2-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static struct platform_driver at91_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .probe = at91_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .remove = at91_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .name = "at91-sama5d2_adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .of_match_table = at91_adc_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .pm = &at91_adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) module_platform_driver(at91_adc_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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