Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Aspeed AST2400/2500 ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ASPEED_RESOLUTION_BITS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ASPEED_CLOCKS_PER_SAMPLE	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ASPEED_REG_ENGINE_CONTROL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ASPEED_REG_INTERRUPT_CONTROL	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ASPEED_REG_VGA_DETECT_CONTROL	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ASPEED_REG_CLOCK_CONTROL	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ASPEED_REG_MAX			0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ASPEED_OPERATION_MODE_POWER_DOWN	(0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ASPEED_OPERATION_MODE_STANDBY		(0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ASPEED_OPERATION_MODE_NORMAL		(0x7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ASPEED_ENGINE_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ASPEED_ADC_CTRL_INIT_RDY	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ASPEED_ADC_INIT_POLLING_TIME	500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ASPEED_ADC_INIT_TIMEOUT		500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct aspeed_adc_model_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	const char *model_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int min_sampling_rate;	// Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int max_sampling_rate;	// Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int vref_voltage;	// mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	bool wait_init_sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct aspeed_adc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	spinlock_t		clk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct clk_hw		*clk_prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct clk_hw		*clk_scaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct reset_control	*rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define ASPEED_CHAN(_idx, _data_reg_addr) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.channel = (_idx),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.address = (_data_reg_addr),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ASPEED_CHAN(0, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ASPEED_CHAN(1, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ASPEED_CHAN(2, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ASPEED_CHAN(3, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ASPEED_CHAN(4, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ASPEED_CHAN(5, 0x1A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ASPEED_CHAN(6, 0x1C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ASPEED_CHAN(7, 0x1E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ASPEED_CHAN(8, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ASPEED_CHAN(9, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ASPEED_CHAN(10, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ASPEED_CHAN(11, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ASPEED_CHAN(12, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ASPEED_CHAN(13, 0x2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ASPEED_CHAN(14, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ASPEED_CHAN(15, 0x2E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			       struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			       int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct aspeed_adc_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	const struct aspeed_adc_model_data *model_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			of_device_get_match_data(data->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		*val = readw(data->base + chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		*val = model_data->vref_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		*val2 = ASPEED_RESOLUTION_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		*val = clk_get_rate(data->clk_scaler->clk) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				ASPEED_CLOCKS_PER_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct aspeed_adc_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	const struct aspeed_adc_model_data *model_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			of_device_get_match_data(data->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (val < model_data->min_sampling_rate ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			val > model_data->max_sampling_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		clk_set_rate(data->clk_scaler->clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				val * ASPEED_CLOCKS_PER_SAMPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		 * Technically, these could be written but the only reasons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 * for doing so seem better handled in userspace.  EPERM is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * returned to signal this is a policy choice rather than a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * hardware limitation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				 unsigned int reg, unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				 unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct aspeed_adc_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	*readval = readl(data->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct iio_info aspeed_adc_iio_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.read_raw = aspeed_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.write_raw = aspeed_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.debugfs_reg_access = aspeed_adc_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int aspeed_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct aspeed_adc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	const struct aspeed_adc_model_data *model_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	const char *clk_parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32 adc_engine_control_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	data->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	platform_set_drvdata(pdev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	data->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (IS_ERR(data->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return PTR_ERR(data->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* Register ADC clock prescaler with source specified by device tree. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	spin_lock_init(&data->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	data->clk_prescaler = clk_hw_register_divider(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				&pdev->dev, "prescaler", clk_parent_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				data->base + ASPEED_REG_CLOCK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				17, 15, 0, &data->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (IS_ERR(data->clk_prescaler))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return PTR_ERR(data->clk_prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * Register ADC clock scaler downstream from the prescaler. Allow rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * setting to adjust the prescaler as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	data->clk_scaler = clk_hw_register_divider(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				&pdev->dev, "scaler", "prescaler",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				data->base + ASPEED_REG_CLOCK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				0, 10, 0, &data->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (IS_ERR(data->clk_scaler)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		ret = PTR_ERR(data->clk_scaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		goto scaler_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (IS_ERR(data->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			"invalid or missing reset controller device tree entry");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		ret = PTR_ERR(data->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		goto reset_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	reset_control_deassert(data->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	model_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (model_data->wait_init_sequence) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		/* Enable engine in normal mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		       data->base + ASPEED_REG_ENGINE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		/* Wait for initial sequence complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					 adc_engine_control_reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					 adc_engine_control_reg_val &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 					 ASPEED_ADC_CTRL_INIT_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 					 ASPEED_ADC_INIT_POLLING_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 					 ASPEED_ADC_INIT_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			goto poll_timeout_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* Start all channels in normal mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = clk_prepare_enable(data->clk_scaler->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		goto clk_enable_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	adc_engine_control_reg_val = GENMASK(31, 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	writel(adc_engine_control_reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		data->base + ASPEED_REG_ENGINE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	model_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	indio_dev->name = model_data->model_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	indio_dev->info = &aspeed_adc_iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	indio_dev->channels = aspeed_adc_iio_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		goto iio_register_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) iio_register_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	writel(ASPEED_OPERATION_MODE_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		data->base + ASPEED_REG_ENGINE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	clk_disable_unprepare(data->clk_scaler->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk_enable_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) poll_timeout_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	reset_control_assert(data->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reset_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	clk_hw_unregister_divider(data->clk_scaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) scaler_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	clk_hw_unregister_divider(data->clk_prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int aspeed_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct aspeed_adc_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	writel(ASPEED_OPERATION_MODE_POWER_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		data->base + ASPEED_REG_ENGINE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	clk_disable_unprepare(data->clk_scaler->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	reset_control_assert(data->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	clk_hw_unregister_divider(data->clk_scaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	clk_hw_unregister_divider(data->clk_prescaler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct aspeed_adc_model_data ast2400_model_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.model_name = "ast2400-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.vref_voltage = 2500, // mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.min_sampling_rate = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.max_sampling_rate = 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct aspeed_adc_model_data ast2500_model_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.model_name = "ast2500-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.vref_voltage = 1800, // mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.min_sampling_rate = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.max_sampling_rate = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.wait_init_sequence = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct of_device_id aspeed_adc_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct platform_driver aspeed_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.probe = aspeed_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.remove = aspeed_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.of_match_table = aspeed_adc_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) module_platform_driver(aspeed_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MODULE_LICENSE("GPL");