Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Analog Devices Generic AXI ADC IP core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2012-2020 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/buffer-dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/fpga/adi-axi-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/adc/adi-axi-adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Register definitions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *   https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* ADC controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ADI_AXI_REG_RSTN			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define   ADI_AXI_REG_RSTN_CE_N			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define   ADI_AXI_REG_RSTN_MMCM_RSTN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define   ADI_AXI_REG_RSTN_RSTN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* ADC Channel controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ADI_AXI_REG_CHAN_CTRL(c)		(0x0400 + (c) * 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define   ADI_AXI_REG_CHAN_CTRL_LB_OWR		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define   ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define   ADI_AXI_REG_CHAN_CTRL_IQCOR_EN	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define   ADI_AXI_REG_CHAN_CTRL_DCFILT_EN	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define   ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define   ADI_AXI_REG_CHAN_CTRL_FMT_TYPE	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   ADI_AXI_REG_CHAN_CTRL_FMT_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define   ADI_AXI_REG_CHAN_CTRL_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 ADI_AXI_REG_CHAN_CTRL_FMT_EN |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 ADI_AXI_REG_CHAN_CTRL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct adi_axi_adc_core_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int				version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) struct adi_axi_adc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct mutex				lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct adi_axi_adc_client		*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	void __iomem				*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct adi_axi_adc_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct list_head			entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct adi_axi_adc_conv			conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct adi_axi_adc_state		*state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct device				*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	const struct adi_axi_adc_core_info	*info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static LIST_HEAD(registered_clients);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static DEFINE_MUTEX(registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return container_of(conv, struct adi_axi_adc_client, conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct adi_axi_adc_client *cl = conv_to_client(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void adi_axi_adc_write(struct adi_axi_adc_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			      unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			      unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	iowrite32(val, st->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				     unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return ioread32(st->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int adi_axi_adc_config_dma_buffer(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 					 struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct iio_buffer *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	const char *dma_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!device_property_present(dev, "dmas"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (device_property_read_string(dev, "dma-names", &dma_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		dma_name = "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	buffer = devm_iio_dmaengine_buffer_alloc(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 						 dma_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (IS_ERR(buffer))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return PTR_ERR(buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	indio_dev->modes |= INDIO_BUFFER_HARDWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	iio_device_attach_buffer(indio_dev, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct adi_axi_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct adi_axi_adc_conv *conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (!conv->read_raw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return conv->read_raw(conv, chan, val, val2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				 struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				 int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct adi_axi_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct adi_axi_adc_conv *conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!conv->write_raw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return conv->write_raw(conv, chan, val, val2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 					const unsigned long *scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct adi_axi_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct adi_axi_adc_conv *conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned int i, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	for (i = 0; i < conv->chip_info->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (test_bit(i, scan_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 							  size_t sizeof_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct adi_axi_adc_client *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	size_t alloc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (sizeof_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		alloc_size += ALIGN(sizeof_priv, IIO_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	cl = kzalloc(alloc_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!cl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mutex_lock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	cl->dev = get_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	list_add_tail(&cl->entry, &registered_clients);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	mutex_unlock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return &cl->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct adi_axi_adc_client *cl = conv_to_client(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	mutex_lock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	list_del(&cl->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	put_device(cl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	mutex_unlock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	kfree(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void devm_adi_axi_adc_conv_release(struct device *dev, void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	adi_axi_adc_conv_unregister(*(struct adi_axi_adc_conv **)res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 							size_t sizeof_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct adi_axi_adc_conv **ptr, *conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ptr = devres_alloc(devm_adi_axi_adc_conv_release, sizeof(*ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	conv = adi_axi_adc_conv_register(dev, sizeof_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (IS_ERR(conv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		devres_free(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return ERR_CAST(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	*ptr = conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	devres_add(dev, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static ssize_t in_voltage_scale_available_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					       struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 					       char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct adi_axi_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct adi_axi_adc_conv *conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	for (i = 0; i < conv->chip_info->num_scales; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		const unsigned int *s = conv->chip_info->scale_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		len += scnprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				 "%u.%06u ", s[0], s[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ADI_AXI_ATTR_SCALE_AVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ADI_AXI_ATTR(_en_, _file_)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	[ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct attribute *adi_axi_adc_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static umode_t axi_adc_attr_is_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				       struct attribute *attr, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct adi_axi_adc_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct adi_axi_adc_conv *conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case ADI_AXI_ATTR_SCALE_AVAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		if (!conv->chip_info->num_scales)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct attribute_group adi_axi_adc_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.attrs = adi_axi_adc_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.is_visible = axi_adc_attr_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct iio_info adi_axi_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.read_raw = &adi_axi_adc_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.write_raw = &adi_axi_adc_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.attrs = &adi_axi_adc_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.update_scan_mode = &adi_axi_adc_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.version = ADI_AXI_PCORE_VER(10, 0, 'a'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	const struct adi_axi_adc_core_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct adi_axi_adc_client *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct device_node *cln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	info = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (!cln) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(dev, "No 'adi,adc-dev' node defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mutex_lock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	list_for_each_entry(cl, &registered_clients, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (!cl->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		if (cl->dev->of_node != cln)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		if (!try_module_get(cl->dev->driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			mutex_unlock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		get_device(cl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		cl->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		mutex_unlock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	mutex_unlock(&registered_clients_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int adi_axi_adc_setup_channels(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				      struct adi_axi_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct adi_axi_adc_conv *conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (conv->preenable_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		ret = conv->preenable_setup(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	for (i = 0; i < conv->chip_info->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				  ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void axi_adc_reset(struct adi_axi_adc_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			  ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void adi_axi_adc_cleanup(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	struct adi_axi_adc_client *cl = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	put_device(cl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	module_put(cl->dev->driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int adi_axi_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct adi_axi_adc_conv *conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	struct adi_axi_adc_client *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	struct adi_axi_adc_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	unsigned int ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	cl = adi_axi_adc_attach_client(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (IS_ERR(cl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return PTR_ERR(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	st->client = cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	cl->state = st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	st->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (IS_ERR(st->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		return PTR_ERR(st->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	conv = &st->client->conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	axi_adc_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (cl->info->version > ver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			"IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			ADI_AXI_PCORE_VER_MINOR(cl->info->version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			ADI_AXI_PCORE_VER_PATCH(cl->info->version),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			ADI_AXI_PCORE_VER_MAJOR(ver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			ADI_AXI_PCORE_VER_MINOR(ver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			ADI_AXI_PCORE_VER_PATCH(ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	indio_dev->info = &adi_axi_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	indio_dev->name = "adi-axi-adc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	indio_dev->num_channels = conv->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	indio_dev->channels = conv->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	ret = adi_axi_adc_setup_channels(&pdev->dev, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	ret = devm_iio_device_register(&pdev->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		 ADI_AXI_PCORE_VER_MAJOR(ver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		 ADI_AXI_PCORE_VER_MINOR(ver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		 ADI_AXI_PCORE_VER_PATCH(ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct of_device_id adi_axi_adc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	{ .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	{ /* end of list */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct platform_driver adi_axi_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		.name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		.of_match_table = adi_axi_adc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	.probe = adi_axi_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) module_platform_driver(adi_axi_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MODULE_LICENSE("GPL v2");