^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog Devices AD9467 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012-2020 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/adc/adi-axi-adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ADI High-Speed ADC common spi interface registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * See Application-Note AN-877:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AN877_ADC_REG_CHIP_PORT_CONF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AN877_ADC_REG_CHIP_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AN877_ADC_REG_CHIP_GRADE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AN877_ADC_REG_CHAN_INDEX 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AN877_ADC_REG_TRANSFER 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AN877_ADC_REG_MODES 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AN877_ADC_REG_TEST_IO 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AN877_ADC_REG_ADC_INPUT 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AN877_ADC_REG_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AN877_ADC_REG_OUTPUT_MODE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AN877_ADC_REG_OUTPUT_ADJUST 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AN877_ADC_REG_OUTPUT_PHASE 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AN877_ADC_REG_OUTPUT_DELAY 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AN877_ADC_REG_VREF 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AN877_ADC_REG_ANALOG_INPUT 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* AN877_ADC_REG_TEST_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AN877_ADC_TESTMODE_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AN877_ADC_TESTMODE_PN23_SEQ 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AN877_ADC_TESTMODE_PN9_SEQ 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AN877_ADC_TESTMODE_USER 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AN877_ADC_TESTMODE_SYNC 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AN877_ADC_TESTMODE_RAMP 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* AN877_ADC_REG_TRANSFER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AN877_ADC_TRANSFER_SYNC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* AN877_ADC_REG_OUTPUT_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* AN877_ADC_REG_OUTPUT_PHASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AN877_ADC_INVERT_DCO_CLK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* AN877_ADC_REG_OUTPUT_DELAY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AN877_ADC_DCO_DELAY_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CHIPID_AD9265 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AD9265_DEF_OUTPUT_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AD9265_REG_VREF_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CHIPID_AD9434 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AD9434_DEF_OUTPUT_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AD9434_REG_VREF_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CHIPID_AD9467 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AD9467_DEF_OUTPUT_MODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AD9467_REG_VREF_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ID_AD9265,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ID_AD9434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ID_AD9467,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct ad9467_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct adi_axi_adc_chip_info axi_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int default_output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int vref_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define to_ad9467_chip_info(_info) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) container_of(_info, struct ad9467_chip_info, axi_adc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ad9467_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int output_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct gpio_desc *pwrdown_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned char tbuf[2], rbuf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) tbuf[0] = 0x80 | (reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tbuf[1] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = spi_write_then_read(spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tbuf, ARRAY_SIZE(tbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rbuf, ARRAY_SIZE(rbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return rbuf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ad9467_spi_write(struct spi_device *spi, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) buf[1] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) buf[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return spi_write(spi, buf, ARRAY_SIZE(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int writeval, unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct spi_device *spi = st->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (readval == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = ad9467_spi_write(spi, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) AN877_ADC_TRANSFER_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = ad9467_spi_read(spi, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *readval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned int ad9265_scale_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned int ad9434_scale_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {1200, 0x0B}, {1180, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const unsigned int ad9467_scale_table[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {2000, 0}, {2100, 6}, {2200, 7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {2300, 8}, {2400, 9}, {2500, 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int *val, unsigned int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const struct adi_axi_adc_chip_info *info = conv->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const struct iio_chan_spec *chan = &info->channels[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmp = (info->scale_table[index][0] * 1000000ULL) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *val = tmp / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *val2 = tmp % 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AD9467_CHAN(_chan, _si, _bits, _sign) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .scan_index = _si, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .sign = _sign, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .realbits = _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct iio_chan_spec ad9434_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AD9467_CHAN(0, 0, 12, 'S'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct iio_chan_spec ad9467_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) AD9467_CHAN(0, 0, 16, 'S'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct ad9467_chip_info ad9467_chip_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [ID_AD9265] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .axi_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .id = CHIPID_AD9265,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .max_rate = 125000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .scale_table = ad9265_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .num_scales = ARRAY_SIZE(ad9265_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .channels = ad9467_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .num_channels = ARRAY_SIZE(ad9467_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .default_output_mode = AD9265_DEF_OUTPUT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .vref_mask = AD9265_REG_VREF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [ID_AD9434] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .axi_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .id = CHIPID_AD9434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .max_rate = 500000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .scale_table = ad9434_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .num_scales = ARRAY_SIZE(ad9434_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .channels = ad9434_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .num_channels = ARRAY_SIZE(ad9434_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .default_output_mode = AD9434_DEF_OUTPUT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .vref_mask = AD9434_REG_VREF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [ID_AD9467] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .axi_adc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .id = CHIPID_AD9467,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .max_rate = 250000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .scale_table = ad9467_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .num_scales = ARRAY_SIZE(ad9467_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .channels = ad9467_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .num_channels = ARRAY_SIZE(ad9467_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .default_output_mode = AD9467_DEF_OUTPUT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .vref_mask = AD9467_REG_VREF_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const struct adi_axi_adc_chip_info *info = conv->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int i, vref_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) vref_val = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) vref_val &= info1->vref_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 0; i < info->num_scales; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (vref_val == info->scale_table[i][1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (i == info->num_scales)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __ad9467_get_scale(conv, i, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const struct adi_axi_adc_chip_info *info = conv->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int scale_val[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < info->num_scales; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (scale_val[0] != val || scale_val[1] != val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ad9467_spi_write(st->spi, AN877_ADC_REG_VREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) info->scale_table[i][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) AN877_ADC_TRANSFER_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int ad9467_read_raw(struct adi_axi_adc_conv *conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return ad9467_get_scale(conv, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *val = clk_get_rate(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int ad9467_write_raw(struct adi_axi_adc_conv *conv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) const struct adi_axi_adc_chip_info *info = conv->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) long r_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ad9467_set_scale(conv, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) r_clk = clk_round_rate(st->clk, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (r_clk < 0 || r_clk > info->max_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_warn(&st->spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "Error setting ADC sample rate %ld", r_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return clk_set_rate(st->clk, r_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) AN877_ADC_TRANSFER_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ad9467_outputmode_set(st->spi, st->output_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void ad9467_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ad9467_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) clk_disable_unprepare(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int ad9467_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const struct ad9467_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct adi_axi_adc_conv *conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct ad9467_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) info = of_device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (IS_ERR(conv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return PTR_ERR(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) st = adi_axi_adc_conv_priv(conv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) st->clk = devm_clk_get(&spi->dev, "adc-clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ERR(st->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return PTR_ERR(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = clk_prepare_enable(st->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = devm_add_action_or_reset(&spi->dev, ad9467_clk_disable, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(st->pwrdown_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return PTR_ERR(st->pwrdown_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (IS_ERR(st->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return PTR_ERR(st->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (st->reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = gpiod_direction_output(st->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spi_set_drvdata(spi, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) conv->chip_info = &info->axi_adc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (id != conv->chip_info->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) id, conv->chip_info->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) conv->reg_access = ad9467_reg_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) conv->write_raw = ad9467_write_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) conv->read_raw = ad9467_read_raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) conv->preenable_setup = ad9467_preenable_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) st->output_mode = info->default_output_mode |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct of_device_id ad9467_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { .compatible = "adi,ad9265", .data = &ad9467_chip_tbl[ID_AD9265], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { .compatible = "adi,ad9434", .data = &ad9467_chip_tbl[ID_AD9434], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_DEVICE_TABLE(of, ad9467_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct spi_driver ad9467_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "ad9467",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .of_match_table = ad9467_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .probe = ad9467_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) module_spi_driver(ad9467_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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