^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * iio/adc/ad799x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010-2011 Michael Hennerich, Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on iio/adc/max1363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008-2010 Jonathan Cameron
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * based on linux/drivers/i2c/chips/max123x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2002-2004 Stefan Eletzhofer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * based on linux/drivers/acron/char/pcf8583.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2000 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ad799x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Support for ad7991, ad7995, ad7999, ad7992, ad7993, ad7994, ad7997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ad7998 and similar chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD799X_CHANNEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * AD7991, AD7995 and AD7999 defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD7991_REF_SEL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD7991_FLTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AD7991_BIT_TRIAL_DELAY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AD7991_SAMPLE_DELAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * AD7992, AD7993, AD7994, AD7997 and AD7998 defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD7998_FLTR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AD7998_ALERT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AD7998_BUSY_ALERT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD7998_BUSY_ALERT_POL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD7998_CONV_RES_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AD7998_ALERT_STAT_REG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AD7998_CONF_REG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AD7998_CYCLE_TMR_REG 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AD7998_DATALOW_REG(x) ((x) * 3 + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD7998_DATAHIGH_REG(x) ((x) * 3 + 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD7998_HYST_REG(x) ((x) * 3 + 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AD7998_CYC_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AD7998_CYC_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD7998_CYC_TCONF_32 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD7998_CYC_TCONF_64 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD7998_CYC_TCONF_128 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AD7998_CYC_TCONF_256 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AD7998_CYC_TCONF_512 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AD7998_CYC_TCONF_1024 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AD7998_CYC_TCONF_2048 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AD7998_ALERT_STAT_CLEAR 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * AD7997 and AD7997 defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AD7997_8_READ_SINGLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AD7997_8_READ_SEQUENCE (BIT(6) | BIT(5) | BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ad7991,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ad7995,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ad7999,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ad7992,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ad7993,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ad7994,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ad7997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ad7998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * struct ad799x_chip_config - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @channel: channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @default_config: device default configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @info: pointer to iio_info struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ad799x_chip_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct iio_chan_spec channel[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 default_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct iio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * struct ad799x_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @num_channels: number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @noirq_config: device configuration w/o IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @irq_config: device configuration w/IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct ad799x_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct ad799x_chip_config noirq_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct ad799x_chip_config irq_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct ad799x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct ad799x_chip_config *chip_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int ad799x_write_config(struct ad799x_state *st, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) switch (st->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case ad7997:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case ad7998:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case ad7992:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case ad7993:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case ad7994:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Will be written when doing a conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) st->config = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int ad799x_read_config(struct ad799x_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) switch (st->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case ad7997:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case ad7998:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case ad7992:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case ad7993:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case ad7994:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* No readback support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return st->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ad799x_update_config(struct ad799x_state *st, u16 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = ad799x_write_config(st, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = ad799x_read_config(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) st->config = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * ad799x_trigger_handler() bh of trigger launched polling to ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Currently there is no option in this driver to disable the saving of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * timestamps within the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static irqreturn_t ad799x_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int b_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) switch (st->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case ad7991:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case ad7995:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case ad7999:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cmd = st->config |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case ad7992:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case ad7993:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case ad7994:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cmd = (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AD7998_CONV_RES_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case ad7997:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case ad7998:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cmd = AD7997_8_READ_SEQUENCE | AD7998_CONV_RES_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) b_sent = i2c_smbus_read_i2c_block_data(st->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cmd, st->transfer_size, st->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (b_sent < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int ad799x_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const unsigned long *scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) kfree(st->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) st->rx_buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!st->rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) st->transfer_size = bitmap_weight(scan_mask, indio_dev->masklength) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) switch (st->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case ad7992:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case ad7993:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case ad7994:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case ad7997:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case ad7998:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) st->config |= (*scan_mask << AD799X_CHANNEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ad799x_write_config(st, st->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int ad799x_scan_direct(struct ad799x_state *st, unsigned ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) switch (st->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case ad7991:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case ad7995:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case ad7999:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cmd = st->config | (BIT(ch) << AD799X_CHANNEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case ad7992:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case ad7993:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case ad7994:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) cmd = BIT(ch) << AD799X_CHANNEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case ad7997:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case ad7998:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cmd = (ch << AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return i2c_smbus_read_word_swapped(st->client, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int ad799x_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = ad799x_scan_direct(st, chan->scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *val = (ret >> chan->scan_type.shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GENMASK(chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = regulator_get_voltage(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const unsigned int ad7998_frequencies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [AD7998_CYC_DIS] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [AD7998_CYC_TCONF_32] = 15625,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [AD7998_CYC_TCONF_64] = 7812,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [AD7998_CYC_TCONF_128] = 3906,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [AD7998_CYC_TCONF_512] = 976,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [AD7998_CYC_TCONF_1024] = 488,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [AD7998_CYC_TCONF_2048] = 244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static ssize_t ad799x_read_frequency(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return sprintf(buf, "%u\n", ad7998_frequencies[ret & AD7998_CYC_MASK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static ssize_t ad799x_write_frequency(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = kstrtol(buf, 10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto error_ret_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Wipe the bits clean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret &= ~AD7998_CYC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < ARRAY_SIZE(ad7998_frequencies); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (val == ad7998_frequencies[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (i == ARRAY_SIZE(ad7998_frequencies)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto error_ret_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = i2c_smbus_write_byte_data(st->client, AD7998_CYCLE_TMR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret | i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto error_ret_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) error_ret_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int ad799x_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!(st->config & AD7998_ALERT_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if ((st->config >> AD799X_CHANNEL_SHIFT) & BIT(chan->scan_index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int ad799x_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) st->config |= BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) st->config &= ~(BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (st->config >> AD799X_CHANNEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) st->config |= AD7998_ALERT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) st->config &= ~AD7998_ALERT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = ad799x_write_config(st, st->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static unsigned int ad799x_threshold_reg(const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enum iio_event_info info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (dir == IIO_EV_DIR_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return AD7998_DATALOW_REG(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return AD7998_DATAHIGH_REG(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case IIO_EV_INFO_HYSTERESIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return AD7998_HYST_REG(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int ad799x_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = i2c_smbus_write_word_swapped(st->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ad799x_threshold_reg(chan, dir, info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) val << chan->scan_type.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int ad799x_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) mutex_lock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = i2c_smbus_read_word_swapped(st->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ad799x_threshold_reg(chan, dir, info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mutex_unlock(&indio_dev->mlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *val = (ret >> chan->scan_type.shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) GENMASK(chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static irqreturn_t ad799x_event_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct ad799x_state *st = iio_priv(private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = i2c_smbus_read_byte_data(st->client, AD7998_ALERT_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (i2c_smbus_write_byte_data(st->client, AD7998_ALERT_STAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) AD7998_ALERT_STAT_CLEAR) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret & BIT(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) i & 0x1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (i >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) IIO_EV_DIR_RISING) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) (i >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ad799x_read_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ad799x_write_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("15625 7812 3906 1953 976 488 244 0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct attribute *ad799x_event_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &iio_dev_attr_sampling_frequency.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct attribute_group ad799x_event_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .attrs = ad799x_event_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct iio_info ad7991_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .read_raw = &ad799x_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .update_scan_mode = ad799x_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct iio_info ad7993_4_7_8_noirq_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .read_raw = &ad799x_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .update_scan_mode = ad799x_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct iio_info ad7993_4_7_8_irq_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .read_raw = &ad799x_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .event_attrs = &ad799x_event_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .read_event_config = &ad799x_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .write_event_config = &ad799x_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .read_event_value = &ad799x_read_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .write_event_value = &ad799x_write_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .update_scan_mode = ad799x_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const struct iio_event_spec ad799x_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define _AD799X_CHANNEL(_index, _realbits, _ev_spec, _num_ev_spec) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .channel = (_index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .scan_index = (_index), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .realbits = (_realbits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .shift = 12 - (_realbits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .event_spec = _ev_spec, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .num_event_specs = _num_ev_spec, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define AD799X_CHANNEL(_index, _realbits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) _AD799X_CHANNEL(_index, _realbits, NULL, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define AD799X_CHANNEL_WITH_EVENTS(_index, _realbits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) _AD799X_CHANNEL(_index, _realbits, ad799x_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ARRAY_SIZE(ad799x_events))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct ad799x_chip_info ad799x_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) [ad7991] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) AD799X_CHANNEL(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) AD799X_CHANNEL(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) AD799X_CHANNEL(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) AD799X_CHANNEL(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .info = &ad7991_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [ad7995] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) AD799X_CHANNEL(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) AD799X_CHANNEL(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) AD799X_CHANNEL(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) AD799X_CHANNEL(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .info = &ad7991_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) [ad7999] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) AD799X_CHANNEL(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) AD799X_CHANNEL(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) AD799X_CHANNEL(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) AD799X_CHANNEL(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .info = &ad7991_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [ad7992] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .num_channels = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) AD799X_CHANNEL(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) AD799X_CHANNEL(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .info = &ad7993_4_7_8_noirq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .irq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) AD799X_CHANNEL_WITH_EVENTS(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) AD799X_CHANNEL_WITH_EVENTS(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .info = &ad7993_4_7_8_irq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [ad7993] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) AD799X_CHANNEL(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) AD799X_CHANNEL(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) AD799X_CHANNEL(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) AD799X_CHANNEL(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .info = &ad7993_4_7_8_noirq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .irq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) AD799X_CHANNEL_WITH_EVENTS(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) AD799X_CHANNEL_WITH_EVENTS(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) AD799X_CHANNEL_WITH_EVENTS(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) AD799X_CHANNEL_WITH_EVENTS(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .info = &ad7993_4_7_8_irq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [ad7994] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) AD799X_CHANNEL(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) AD799X_CHANNEL(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) AD799X_CHANNEL(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) AD799X_CHANNEL(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .info = &ad7993_4_7_8_noirq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .irq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) AD799X_CHANNEL_WITH_EVENTS(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) AD799X_CHANNEL_WITH_EVENTS(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) AD799X_CHANNEL_WITH_EVENTS(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) AD799X_CHANNEL_WITH_EVENTS(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .info = &ad7993_4_7_8_irq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [ad7997] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .num_channels = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) AD799X_CHANNEL(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) AD799X_CHANNEL(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) AD799X_CHANNEL(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) AD799X_CHANNEL(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) AD799X_CHANNEL(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) AD799X_CHANNEL(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) AD799X_CHANNEL(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) AD799X_CHANNEL(7, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .info = &ad7993_4_7_8_noirq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .irq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) AD799X_CHANNEL_WITH_EVENTS(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) AD799X_CHANNEL_WITH_EVENTS(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) AD799X_CHANNEL_WITH_EVENTS(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) AD799X_CHANNEL_WITH_EVENTS(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) AD799X_CHANNEL(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) AD799X_CHANNEL(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) AD799X_CHANNEL(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) AD799X_CHANNEL(7, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .info = &ad7993_4_7_8_irq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) [ad7998] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .num_channels = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .noirq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) AD799X_CHANNEL(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) AD799X_CHANNEL(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) AD799X_CHANNEL(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) AD799X_CHANNEL(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) AD799X_CHANNEL(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) AD799X_CHANNEL(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) AD799X_CHANNEL(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) AD799X_CHANNEL(7, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .info = &ad7993_4_7_8_noirq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .irq_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .channel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) AD799X_CHANNEL_WITH_EVENTS(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) AD799X_CHANNEL_WITH_EVENTS(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) AD799X_CHANNEL_WITH_EVENTS(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) AD799X_CHANNEL_WITH_EVENTS(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) AD799X_CHANNEL(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) AD799X_CHANNEL(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) AD799X_CHANNEL(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) AD799X_CHANNEL(7, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .info = &ad7993_4_7_8_irq_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int ad799x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct ad799x_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) const struct ad799x_chip_info *chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) &ad799x_chip_info_tbl[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* this is only used for device removal purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) st->id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (client->irq > 0 && chip_info->irq_config.info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) st->chip_config = &chip_info->irq_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) st->chip_config = &chip_info->noirq_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* TODO: Add pdata options for filtering and bit delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) st->reg = devm_regulator_get(&client->dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) st->vref = devm_regulator_get(&client->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (IS_ERR(st->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = PTR_ERR(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = regulator_enable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) st->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) indio_dev->info = st->chip_config->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) indio_dev->channels = st->chip_config->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) indio_dev->num_channels = chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = ad799x_update_config(st, st->chip_config->default_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto error_disable_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &ad799x_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto error_disable_vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = devm_request_threaded_irq(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ad799x_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) goto error_cleanup_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) goto error_cleanup_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) error_cleanup_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) error_disable_vref:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int ad799x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) kfree(st->rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int __maybe_unused ad799x_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int __maybe_unused ad799x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct ad799x_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_err(dev, "Unable to enable vcc regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = regulator_enable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_err(dev, "Unable to enable vref regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* resync config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = ad799x_update_config(st, st->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static SIMPLE_DEV_PM_OPS(ad799x_pm_ops, ad799x_suspend, ad799x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const struct i2c_device_id ad799x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) { "ad7991", ad7991 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) { "ad7995", ad7995 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { "ad7999", ad7999 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { "ad7992", ad7992 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { "ad7993", ad7993 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) { "ad7994", ad7994 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) { "ad7997", ad7997 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { "ad7998", ad7998 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MODULE_DEVICE_TABLE(i2c, ad799x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct i2c_driver ad799x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .name = "ad799x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .pm = &ad799x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .probe = ad799x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .remove = ad799x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .id_table = ad799x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) module_i2c_driver(ad799x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) MODULE_DESCRIPTION("Analog Devices AD799x ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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