Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* ad7949.c - Analog Devices ADC driver 14/16 bits 4/8 channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2018 CMC NV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * https://www.analog.com/media/en/technical-documentation/data-sheets/AD7949.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AD7949_MASK_CHANNEL_SEL		GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AD7949_MASK_TOTAL		GENMASK(13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AD7949_OFFSET_CHANNEL_SEL	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AD7949_CFG_READ_BACK		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AD7949_CFG_REG_SIZE_BITS	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	ID_AD7949 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	ID_AD7682,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	ID_AD7689,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct ad7949_adc_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u8 num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u8 resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static const struct ad7949_adc_spec ad7949_adc_spec[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	[ID_AD7949] = { .num_channels = 8, .resolution = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	[ID_AD7682] = { .num_channels = 4, .resolution = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	[ID_AD7689] = { .num_channels = 8, .resolution = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * struct ad7949_adc_chip - AD ADC chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * @lock: protects write sequences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @vref: regulator generating Vref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @indio_dev: reference to iio structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @spi: reference to spi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @resolution: resolution of the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @cfg: copy of the configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @current_channel: current channel in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * @buffer: buffer to send / receive data to / from device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct ad7949_adc_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u8 resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u16 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int current_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u16 buffer ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int bits_per_word = ad7949_adc->resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int shift = bits_per_word - AD7949_CFG_REG_SIZE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct spi_transfer tx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			.tx_buf = &ad7949_adc->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			.bits_per_word = bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ad7949_adc->buffer = ad7949_adc->cfg << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	spi_message_init_with_transfers(&msg, tx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ret = spi_sync(ad7949_adc->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * This delay is to avoid a new request before the required time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * send a new command to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				   unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int bits_per_word = ad7949_adc->resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int mask = GENMASK(ad7949_adc->resolution - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct spi_transfer tx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			.rx_buf = &ad7949_adc->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			.bits_per_word = bits_per_word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 * 1: write CFG for sample N and read old data (sample N-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * 2: if CFG was not changed since sample N-1 then we'll get good data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 *    at the next xfer, so we bail out now, otherwise we write something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 *    and we read garbage (sample N-1 configuration).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		ret = ad7949_spi_write_cfg(ad7949_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 					   channel << AD7949_OFFSET_CHANNEL_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					   AD7949_MASK_CHANNEL_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (channel == ad7949_adc->current_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* 3: write something and read actual data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	ad7949_adc->buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	spi_message_init_with_transfers(&msg, tx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ret = spi_sync(ad7949_adc->spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * This delay is to avoid a new request before the required time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * send a new command to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ad7949_adc->current_channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	*val = ad7949_adc->buffer & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AD7949_ADC_CHANNEL(chan) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.channel = (chan),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct iio_chan_spec ad7949_adc_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	AD7949_ADC_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	AD7949_ADC_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	AD7949_ADC_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	AD7949_ADC_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	AD7949_ADC_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	AD7949_ADC_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	AD7949_ADC_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	AD7949_ADC_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ad7949_spi_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			   int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		mutex_lock(&ad7949_adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		ret = ad7949_spi_read_channel(ad7949_adc, val, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		mutex_unlock(&ad7949_adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		ret = regulator_get_voltage(ad7949_adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		*val = ret / 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int ad7949_spi_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			unsigned int reg, unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		*readval = ad7949_adc->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ret = ad7949_spi_write_cfg(ad7949_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			writeval & AD7949_MASK_TOTAL, AD7949_MASK_TOTAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct iio_info ad7949_spi_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.read_raw = ad7949_spi_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.debugfs_reg_access = ad7949_spi_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ad7949_spi_init(struct ad7949_adc_chip *ad7949_adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Sequencer disabled, CFG readback disabled, IN0 as default channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ad7949_adc->current_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ret = ad7949_spi_write_cfg(ad7949_adc, 0x3C79, AD7949_MASK_TOTAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * Do two dummy conversions to apply the first configuration setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 * Required only after the start up of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ad7949_spi_read_channel(ad7949_adc, &val, ad7949_adc->current_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int ad7949_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	const struct ad7949_adc_spec *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct ad7949_adc_chip *ad7949_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	indio_dev = devm_iio_device_alloc(dev, sizeof(*ad7949_adc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		dev_err(dev, "can not allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	indio_dev->info = &ad7949_spi_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	indio_dev->channels = ad7949_adc_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ad7949_adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ad7949_adc->indio_dev = indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ad7949_adc->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	spec = &ad7949_adc_spec[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	indio_dev->num_channels = spec->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ad7949_adc->resolution = spec->resolution;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	ad7949_adc->vref = devm_regulator_get(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (IS_ERR(ad7949_adc->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev_err(dev, "fail to request regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return PTR_ERR(ad7949_adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ret = regulator_enable(ad7949_adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		dev_err(dev, "fail to enable regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	mutex_init(&ad7949_adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ret = ad7949_spi_init(ad7949_adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		dev_err(dev, "enable to init this device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		dev_err(dev, "fail to register iio device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	mutex_destroy(&ad7949_adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	regulator_disable(ad7949_adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int ad7949_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct ad7949_adc_chip *ad7949_adc = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	mutex_destroy(&ad7949_adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	regulator_disable(ad7949_adc->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct of_device_id ad7949_spi_of_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ .compatible = "adi,ad7949" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ .compatible = "adi,ad7682" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ .compatible = "adi,ad7689" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_DEVICE_TABLE(of, ad7949_spi_of_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct spi_device_id ad7949_spi_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	{ "ad7949", ID_AD7949  },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	{ "ad7682", ID_AD7682 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{ "ad7689", ID_AD7689 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_DEVICE_TABLE(spi, ad7949_spi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct spi_driver ad7949_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.name		= "ad7949",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.of_match_table	= ad7949_spi_of_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.probe	  = ad7949_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.remove   = ad7949_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.id_table = ad7949_spi_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) module_spi_driver(ad7949_spi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@essensium.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_DESCRIPTION("Analog Devices 14/16-bit 8-channel ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_LICENSE("GPL v2");