Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2012 CS Systemes d'Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD7923_WRITE_CR		BIT(11)		/* write control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD7923_RANGE		BIT(1)		/* range to REFin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD7923_CODING		BIT(0)		/* coding is straight binary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AD7923_PM_MODE_AS	(1)		/* auto shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD7923_PM_MODE_FS	(2)		/* full shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD7923_PM_MODE_OPS	(3)		/* normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD7923_SEQUENCE_OFF	(0)		/* no sequence fonction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD7923_SEQUENCE_PROTECT	(2)		/* no interrupt write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD7923_SEQUENCE_ON	(3)		/* continuous sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AD7923_PM_MODE_WRITE(mode)	((mode) << 4)	 /* write mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AD7923_CHANNEL_WRITE(channel)	((channel) << 6) /* write channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AD7923_SEQUENCE_WRITE(sequence)	((((sequence) & 1) << 3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 					+ (((sequence) & 2) << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 						/* write sequence fonction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* left shift for CR : bit 11 transmit in first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AD7923_SHIFT_REGISTER	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* val = value, dec = left shift, bits = number of bits of the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define EXTRACT(val, dec, bits)		(((val) >> (dec)) & ((1 << (bits)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct ad7923_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct spi_transfer		ring_xfer[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct spi_transfer		scan_single_xfer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct spi_message		ring_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct spi_message		scan_single_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct regulator		*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned int			settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * Length = 8 channels + 4 extra for 8 byte timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	__be16				rx_buf[12] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__be16				tx_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct ad7923_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) enum ad7923_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	AD7904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	AD7914,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	AD7924,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	AD7908,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	AD7918,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	AD7928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AD7923_V_CHAN(index, bits)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.channel = index,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.address = index,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.scan_index = index,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			.realbits = (bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			.storagebits = 16,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			.endianness = IIO_BE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DECLARE_AD7923_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	AD7923_V_CHAN(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	AD7923_V_CHAN(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	AD7923_V_CHAN(2, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	AD7923_V_CHAN(3, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	IIO_CHAN_SOFT_TIMESTAMP(4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DECLARE_AD7908_CHANNELS(name, bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct iio_chan_spec name ## _channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	AD7923_V_CHAN(0, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	AD7923_V_CHAN(1, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	AD7923_V_CHAN(2, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	AD7923_V_CHAN(3, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	AD7923_V_CHAN(4, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	AD7923_V_CHAN(5, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	AD7923_V_CHAN(6, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	AD7923_V_CHAN(7, bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	IIO_CHAN_SOFT_TIMESTAMP(8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static DECLARE_AD7923_CHANNELS(ad7904, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static DECLARE_AD7923_CHANNELS(ad7914, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static DECLARE_AD7923_CHANNELS(ad7924, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static DECLARE_AD7908_CHANNELS(ad7908, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static DECLARE_AD7908_CHANNELS(ad7918, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static DECLARE_AD7908_CHANNELS(ad7928, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct ad7923_chip_info ad7923_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	[AD7904] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.channels = ad7904_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.num_channels = ARRAY_SIZE(ad7904_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	[AD7914] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.channels = ad7914_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.num_channels = ARRAY_SIZE(ad7914_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	[AD7924] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.channels = ad7924_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.num_channels = ARRAY_SIZE(ad7924_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	[AD7908] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.channels = ad7908_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.num_channels = ARRAY_SIZE(ad7908_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	[AD7918] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.channels = ad7918_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.num_channels = ARRAY_SIZE(ad7918_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	[AD7928] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.channels = ad7928_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.num_channels = ARRAY_SIZE(ad7928_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				   const unsigned long *active_scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct ad7923_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int i, cmd, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * For this driver the last channel is always the software timestamp so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 * skip that one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			st->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		cmd <<= AD7923_SHIFT_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		st->tx_buf[len++] = cpu_to_be16(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* build spi ring message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	st->ring_xfer[0].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	st->ring_xfer[0].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	spi_message_init(&st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		st->ring_xfer[i + 1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		st->ring_xfer[i + 1].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* make sure last transfer cs_change is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	st->ring_xfer[i + 1].cs_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * ad7923_trigger_handler() bh of trigger launched polling to ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * Currently there is no option in this driver to disable the saving of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * timestamps within the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static irqreturn_t ad7923_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct ad7923_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int b_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	b_sent = spi_sync(st->spi, &st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (b_sent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 					   iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	int ret, cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		st->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	cmd <<= AD7923_SHIFT_REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	st->tx_buf[0] = cpu_to_be16(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ret = spi_sync(st->spi, &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return be16_to_cpu(st->rx_buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int ad7923_get_range(struct ad7923_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	vref = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (vref < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	vref /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!(st->settings & AD7923_RANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		vref *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int ad7923_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			   int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			   int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			   long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct ad7923_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		ret = ad7923_scan_direct(st, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (chan->address == EXTRACT(ret, 12, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			*val = EXTRACT(ret, 0, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ret = ad7923_get_range(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		*val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct iio_info ad7923_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.read_raw = &ad7923_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.update_scan_mode = ad7923_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int ad7923_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct ad7923_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	const struct ad7923_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	st->settings = AD7923_CODING | AD7923_RANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	indio_dev->channels = info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	indio_dev->num_channels = info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	indio_dev->info = &ad7923_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* Setup default message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	st->scan_single_xfer[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	st->scan_single_xfer[0].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	st->scan_single_xfer[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	spi_message_init(&st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	st->reg = devm_regulator_get(&spi->dev, "refin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 					 &ad7923_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		goto error_cleanup_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) error_cleanup_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int ad7923_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct ad7923_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct spi_device_id ad7923_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	{"ad7904", AD7904},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{"ad7914", AD7914},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{"ad7923", AD7924},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	{"ad7924", AD7924},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{"ad7908", AD7908},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	{"ad7918", AD7918},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	{"ad7928", AD7928},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_DEVICE_TABLE(spi, ad7923_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct of_device_id ad7923_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	{ .compatible = "adi,ad7904", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	{ .compatible = "adi,ad7914", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	{ .compatible = "adi,ad7923", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	{ .compatible = "adi,ad7924", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	{ .compatible = "adi,ad7908", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{ .compatible = "adi,ad7918", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{ .compatible = "adi,ad7928", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_DEVICE_TABLE(of, ad7923_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct spi_driver ad7923_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		.name	= "ad7923",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		.of_match_table = ad7923_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.probe		= ad7923_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.remove		= ad7923_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.id_table	= ad7923_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) module_spi_driver(ad7923_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_LICENSE("GPL v2");