Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD7887 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2010-2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/platform_data/ad7887.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD7887_REF_DIS		BIT(5)	/* on-chip reference disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AD7887_DUAL		BIT(4)	/* dual-channel mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD7887_CH_AIN1		BIT(3)	/* convert on channel 1, DUAL=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD7887_CH_AIN0		0	/* convert on channel 0, DUAL=0,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD7887_PM_MODE1		0	/* CS based shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD7887_PM_MODE2		1	/* full on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD7887_PM_MODE3		2	/* auto shutdown after conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AD7887_PM_MODE4		3	/* standby mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) enum ad7887_channels {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	AD7887_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	AD7887_CH0_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	AD7887_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * struct ad7887_chip_info - chip specifc information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @int_vref_mv:	the internal reference voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @channels:		channels specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * @num_channels:	number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * @dual_channels:	channels specification in dual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * @num_dual_channels:	number of channels in dual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct ad7887_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u16				int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	const struct iio_chan_spec	*channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int			num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	const struct iio_chan_spec	*dual_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int			num_dual_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct ad7887_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	const struct ad7887_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct regulator		*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct spi_transfer		xfer[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct spi_message		msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct spi_message		*ring_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned char			tx_cmd_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * Buffer needs to be large enough to hold two 16 bit samples and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * 64 bit aligned 64 bit timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) enum ad7887_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	ID_AD7887
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static int ad7887_ring_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct ad7887_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* We know this is a single long so can 'cheat' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	switch (*indio_dev->active_scan_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case (1 << 0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		st->ring_msg = &st->msg[AD7887_CH0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case (1 << 1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		st->ring_msg = &st->msg[AD7887_CH1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		/* Dummy read: push CH1 setting down to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		spi_sync(st->spi, st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case ((1 << 1) | (1 << 0)):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		st->ring_msg = &st->msg[AD7887_CH0_CH1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct ad7887_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* dummy read: restore default CH0 settin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * ad7887_trigger_handler() bh of trigger launched polling to ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * Currently there is no option in this driver to disable the saving of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * timestamps within the ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static irqreturn_t ad7887_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct ad7887_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int b_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	b_sent = spi_sync(st->spi, st->ring_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (b_sent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.preenable = &ad7887_ring_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.postdisable = &ad7887_ring_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret = spi_sync(st->spi, &st->msg[ch]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int ad7887_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			   int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			   int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			   long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct ad7887_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		ret = ad7887_scan_direct(st, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		*val = ret >> chan->scan_type.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		*val &= GENMASK(chan->scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (st->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			*val = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			if (*val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				return *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			*val /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			*val = st->chip_info->int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AD7887_CHANNEL(x) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.channel = (x), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.address = (x), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.scan_index = (x), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.shift = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct iio_chan_spec ad7887_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	AD7887_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct iio_chan_spec ad7887_dual_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	AD7887_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	AD7887_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	IIO_CHAN_SOFT_TIMESTAMP(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * More devices added in future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	[ID_AD7887] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.channels = ad7887_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.num_channels = ARRAY_SIZE(ad7887_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.dual_channels = ad7887_dual_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.int_vref_mv = 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct iio_info ad7887_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.read_raw = &ad7887_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int ad7887_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct ad7887_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct ad7887_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	uint8_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (!pdata || !pdata->use_onchip_ref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		st->reg = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	st->chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	indio_dev->info = &ad7887_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* Setup default message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	mode = AD7887_PM_MODE4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!pdata || !pdata->use_onchip_ref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		mode |= AD7887_REF_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (pdata && pdata->en_dual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		mode |= AD7887_DUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	st->xfer[0].rx_buf = &st->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	st->xfer[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	spi_message_init(&st->msg[AD7887_CH0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (pdata && pdata->en_dual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		st->xfer[1].rx_buf = &st->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		st->xfer[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		st->xfer[2].rx_buf = &st->data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		st->xfer[2].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		spi_message_init(&st->msg[AD7887_CH0_CH1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		st->xfer[3].rx_buf = &st->data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		st->xfer[3].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		spi_message_init(&st->msg[AD7887_CH1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		indio_dev->channels = st->chip_info->dual_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		indio_dev->num_channels = st->chip_info->num_dual_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			&ad7887_trigger_handler, &ad7887_ring_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		goto error_unregister_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) error_unregister_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (st->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int ad7887_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct ad7887_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (st->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct spi_device_id ad7887_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	{"ad7887", ID_AD7887},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_DEVICE_TABLE(spi, ad7887_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct spi_driver ad7887_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.name	= "ad7887",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.probe		= ad7887_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.remove		= ad7887_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.id_table	= ad7887_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) module_spi_driver(ad7887_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_LICENSE("GPL v2");