^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011-2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/adc/ad_sigma_delta.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/ad7793.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * (AD7792)/24-bit (AD7793)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Communications Register Bit Designations (AD7793_REG_COMM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD7793_COMM_WEN (1 << 7) /* Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD7793_COMM_READ (1 << 6) /* Read Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Status Register Bit Designations (AD7793_REG_STAT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AD7793_STAT_RDY (1 << 7) /* Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Mode Register Bit Designations (AD7793_REG_MODE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AD7793_MODE_IDLE 2 /* Idle Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * available at the CLK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * at the CLK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Configuration Register Bit Designations (AD7793_REG_CONF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Generator Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AD7793_CH_TEMP 6 /* Temp Sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* ID Register Bit Designations (AD7793_REG_ID) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AD7785_ID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AD7792_ID 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AD7793_ID 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AD7794_ID 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AD7795_ID 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AD7796_ID 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AD7797_ID 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AD7798_ID 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AD7799_ID 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AD7793_ID_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * IEXC2 connect to IOUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * IEXC2 connect to IOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * IEXC1,2 connect to IOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * IEXC1,2 connect to IOUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * In order to avoid contentions on the SPI bus, it's therefore necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * to use spi bus locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AD7793_FLAG_HAS_CLKSEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AD7793_FLAG_HAS_REFSEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AD7793_FLAG_HAS_VBIAS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AD7793_HAS_EXITATION_CURRENT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AD7793_FLAG_HAS_GAIN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AD7793_FLAG_HAS_BUFFER BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ad7793_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct iio_info *iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const u16 *sample_freq_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ad7793_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct ad7793_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u16 int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u16 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 scale_avail[8][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ad_sigma_delta sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum ad7793_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ID_AD7785,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ID_AD7792,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ID_AD7793,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ID_AD7794,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ID_AD7795,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ID_AD7796,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ID_AD7797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ID_AD7798,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ID_AD7799,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return container_of(sd, struct ad7793_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) st->conf &= ~AD7793_CONF_CHAN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) st->conf |= AD7793_CONF_CHAN(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int ad7793_set_mode(struct ad_sigma_delta *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum ad_sigma_delta_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) st->mode &= ~AD7793_MODE_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) st->mode |= AD7793_MODE_SEL(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .set_channel = ad7793_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .set_mode = ad7793_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .has_registers = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .addr_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .read_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .irq_flags = IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int ad7793_calibrate_all(struct ad7793_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ARRAY_SIZE(ad7793_calib_arr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ad7793_check_platform_data(struct ad7793_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct ad7793_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ((pdata->exitation_current != AD7793_IX_10uA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (pdata->exitation_current != AD7793_IX_210uA)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pdata->clock_src != AD7793_CLK_SRC_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pdata->refsel != AD7793_REFSEL_REFIN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pdata->exitation_current != AD7793_IX_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int ad7793_setup(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const struct ad7793_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int vref_mv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ad7793_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long long scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = ad7793_check_platform_data(st, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* reset the serial interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = ad_sd_reset(&st->sd, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) usleep_range(500, 2000); /* Wait for at least 500us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* write/read test for device presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) id &= AD7793_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (id != st->chip_info->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(&st->sd.spi->dev, "device ID query failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) st->mode = AD7793_MODE_RATE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) st->conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) st->conf |= AD7793_CONF_BUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (pdata->boost_enable &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) st->conf |= AD7793_CONF_BOOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (pdata->burnout_current)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) st->conf |= AD7793_CONF_BO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (pdata->unipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) st->conf |= AD7793_CONF_UNIPOLAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) st->conf |= AD7793_CONF_GAIN(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = ad7793_set_channel(&st->sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pdata->exitation_current |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (pdata->current_source_direction << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = ad7793_calibrate_all(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Populate available ADC input ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) scale_uv = ((u64)vref_mv * 100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) >> (st->chip_info->channels[0].scan_type.realbits -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) scale_uv >>= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) st->scale_avail[i][0] = scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(&st->sd.spi->dev, "setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 33, 19, 17, 16, 12, 10, 8, 6, 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 33, 0, 17, 16, 12, 10, 8, 6, 4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int ad7793_read_avail(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const int **vals, int *type, int *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct ad7793_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *vals = (int *)st->scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *type = IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Values are stored in a 2D matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *length = ARRAY_SIZE(st->scale_avail) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct attribute *ad7793_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) &iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct attribute_group ad7793_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .attrs = ad7793_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct attribute *ad7797_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct attribute_group ad7797_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .attrs = ad7797_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int ad7793_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct ad7793_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long long scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (chan->differential) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *val = st->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) scale_avail[(st->conf >> 8) & 0x7][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *val2 = st->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) scale_avail[(st->conf >> 8) & 0x7][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* 1170mV / 2^23 * 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) scale_uv = (1170ULL * 1000000000ULL * 6ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* 1170mV / 0.81 mV/C / 2^23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) scale_uv = 1444444444444444ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *val2 = scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!unipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *val = -(1 << (chan->scan_type.realbits - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Kelvin to Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (chan->type == IIO_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) offset = 273ULL << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) do_div(offset, 1444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *val -= offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *val = st->chip_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int ad7793_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct ad7793_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (val2 == st->scale_avail[i][1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tmp = st->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) st->conf &= ~AD7793_CONF_GAIN(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) st->conf |= AD7793_CONF_GAIN(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (tmp == st->conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sizeof(st->conf), st->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ad7793_calibrate_all(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (val == st->chip_info->sample_freq_avail[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (i == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) st->mode &= ~AD7793_MODE_RATE(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) st->mode |= AD7793_MODE_RATE(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct iio_info ad7793_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .read_raw = &ad7793_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .write_raw = &ad7793_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .read_avail = ad7793_read_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .attrs = &ad7793_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .validate_trigger = ad_sd_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct iio_info ad7797_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .read_raw = &ad7793_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .write_raw = &ad7793_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .attrs = &ad7797_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .validate_trigger = ad_sd_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) _storagebits, _shift, _extend_name, _type, _mask_type_av, _mask_all) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .type = (_type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .differential = (_channel2 == -1 ? 0 : 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .channel = (_channel1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .channel2 = (_channel2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .address = (_address), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .extend_name = (_extend_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .info_mask_shared_by_type_available = (_mask_type_av), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .info_mask_shared_by_all = _mask_all, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .scan_index = (_si), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .realbits = (_bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .storagebits = (_storagebits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .shift = (_shift), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define AD7793_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) _storagebits, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) _storagebits, _shift, NULL, IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define AD7793_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) _storagebits, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) _storagebits, _shift, "shorted", IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define AD7793_TEMP_CHANNEL(_si, _address, _bits, _storagebits, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __AD7793_CHANNEL(_si, 0, -1, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) _storagebits, _shift, NULL, IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define AD7793_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) __AD7793_CHANNEL(_si, _channel, -1, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) _storagebits, _shift, "supply", IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define AD7797_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) _storagebits, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __AD7793_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) _storagebits, _shift, NULL, IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define AD7797_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) _storagebits, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) __AD7793_CHANNEL(_si, _channel, _channel, _address, _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) _storagebits, _shift, "shorted", IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) const struct iio_chan_spec _name##_channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) AD7793_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) AD7793_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) IIO_CHAN_SOFT_TIMESTAMP(6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const struct iio_chan_spec _name##_channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) AD7793_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) AD7793_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) AD7793_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) AD7793_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) AD7793_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) AD7793_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) IIO_CHAN_SOFT_TIMESTAMP(9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const struct iio_chan_spec _name##_channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) AD7797_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) AD7797_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) AD7793_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) AD7793_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) IIO_CHAN_SOFT_TIMESTAMP(4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const struct iio_chan_spec _name##_channels[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) AD7793_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) AD7793_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) AD7793_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) AD7793_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) AD7793_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) IIO_CHAN_SOFT_TIMESTAMP(5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [ID_AD7785] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .id = AD7785_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .channels = ad7785_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .num_channels = ARRAY_SIZE(ad7785_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .flags = AD7793_FLAG_HAS_CLKSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) AD7793_FLAG_HAS_REFSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) AD7793_FLAG_HAS_VBIAS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) AD7793_HAS_EXITATION_CURRENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [ID_AD7792] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .id = AD7792_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .channels = ad7792_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .num_channels = ARRAY_SIZE(ad7792_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .flags = AD7793_FLAG_HAS_CLKSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) AD7793_FLAG_HAS_REFSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) AD7793_FLAG_HAS_VBIAS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) AD7793_HAS_EXITATION_CURRENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [ID_AD7793] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .id = AD7793_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .channels = ad7793_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .num_channels = ARRAY_SIZE(ad7793_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .flags = AD7793_FLAG_HAS_CLKSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) AD7793_FLAG_HAS_REFSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) AD7793_FLAG_HAS_VBIAS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) AD7793_HAS_EXITATION_CURRENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [ID_AD7794] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .id = AD7794_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .channels = ad7794_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .num_channels = ARRAY_SIZE(ad7794_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .flags = AD7793_FLAG_HAS_CLKSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) AD7793_FLAG_HAS_REFSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) AD7793_FLAG_HAS_VBIAS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) AD7793_HAS_EXITATION_CURRENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [ID_AD7795] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .id = AD7795_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .channels = ad7795_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .num_channels = ARRAY_SIZE(ad7795_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .flags = AD7793_FLAG_HAS_CLKSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) AD7793_FLAG_HAS_REFSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) AD7793_FLAG_HAS_VBIAS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) AD7793_HAS_EXITATION_CURRENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [ID_AD7796] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .id = AD7796_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .channels = ad7796_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .num_channels = ARRAY_SIZE(ad7796_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .iio_info = &ad7797_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .sample_freq_avail = ad7797_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .flags = AD7793_FLAG_HAS_CLKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [ID_AD7797] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .id = AD7797_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .channels = ad7797_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .num_channels = ARRAY_SIZE(ad7797_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .iio_info = &ad7797_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .sample_freq_avail = ad7797_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .flags = AD7793_FLAG_HAS_CLKSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [ID_AD7798] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .id = AD7798_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .channels = ad7798_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .num_channels = ARRAY_SIZE(ad7798_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .flags = AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [ID_AD7799] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .id = AD7799_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .channels = ad7799_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .num_channels = ARRAY_SIZE(ad7799_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .iio_info = &ad7793_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .sample_freq_avail = ad7793_sample_freq_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .flags = AD7793_FLAG_HAS_GAIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) AD7793_FLAG_HAS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int ad7793_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) const struct ad7793_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct ad7793_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) int ret, vref_mv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_err(&spi->dev, "no platform data?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(&spi->dev, "no IRQ?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) st->reg = devm_regulator_get(&spi->dev, "refin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) vref_mv = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (vref_mv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) vref_mv /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) vref_mv = 1170; /* Build-in ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) st->chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) indio_dev->info = st->chip_info->iio_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = ad_sd_setup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = ad7793_setup(indio_dev, pdata, vref_mv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) goto error_remove_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) goto error_remove_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) error_remove_trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (pdata->refsel != AD7793_REFSEL_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int ad7793_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) const struct ad7793_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct ad7793_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (pdata->refsel != AD7793_REFSEL_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const struct spi_device_id ad7793_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {"ad7785", ID_AD7785},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {"ad7792", ID_AD7792},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {"ad7793", ID_AD7793},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {"ad7794", ID_AD7794},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {"ad7795", ID_AD7795},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {"ad7796", ID_AD7796},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {"ad7797", ID_AD7797},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {"ad7798", ID_AD7798},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {"ad7799", ID_AD7799},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_DEVICE_TABLE(spi, ad7793_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct spi_driver ad7793_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "ad7793",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .probe = ad7793_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .remove = ad7793_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .id_table = ad7793_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) module_spi_driver(ad7793_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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