Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD7170/AD7171 and AD7780/AD7781 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2019 Renato Lui Geh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/adc/ad_sigma_delta.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD7780_RDY		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD7780_FILTER		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD7780_ERR		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AD7780_ID1		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD7780_ID0		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD7780_GAIN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD7170_ID		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD7171_ID		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AD7780_ID		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AD7781_ID		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AD7780_ID_MASK		(AD7780_ID0 | AD7780_ID1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AD7780_PATTERN_GOOD	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AD7780_PATTERN_MASK	GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AD7170_PATTERN_GOOD	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AD7170_PATTERN_MASK	GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AD7780_GAIN_MIDPOINT	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AD7780_FILTER_MIDPOINT	13350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static const unsigned int ad778x_gain[2]      = { 1, 128 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static const unsigned int ad778x_odr_avail[2] = { 10000, 16700 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct ad7780_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct iio_chan_spec	channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int		pattern_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned int		pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	bool			is_ad778x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct ad7780_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	const struct ad7780_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct regulator		*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct gpio_desc		*powerdown_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct gpio_desc		*gain_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct gpio_desc		*filter_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned int			gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int			odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int			int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct ad_sigma_delta sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) enum ad7780_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ID_AD7170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ID_AD7171,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ID_AD7780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	ID_AD7781,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static struct ad7780_state *ad_sigma_delta_to_ad7780(struct ad_sigma_delta *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return container_of(sd, struct ad7780_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static int ad7780_set_mode(struct ad_sigma_delta *sigma_delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			   enum ad_sigma_delta_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct ad7780_state *st = ad_sigma_delta_to_ad7780(sigma_delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case AD_SD_MODE_SINGLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	case AD_SD_MODE_CONTINUOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	gpiod_set_value(st->powerdown_gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int ad7780_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			   int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			   int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			   long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct ad7780_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int voltage_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return ad_sigma_delta_single_conversion(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		voltage_uv = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (voltage_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			return voltage_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		voltage_uv /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		*val = voltage_uv * st->gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		*val2 = chan->scan_type.realbits - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		st->int_vref_mv = voltage_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		*val = -(1 << (chan->scan_type.realbits - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		*val = st->odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ad7780_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			    int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			    int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			    long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct ad7780_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	const struct ad7780_chip_info *chip_info = st->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned long long vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned int full_scale, gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (!chip_info->is_ad778x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		vref = st->int_vref_mv * 1000000LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		full_scale = 1 << (chip_info->channel.scan_type.realbits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		gain = DIV_ROUND_CLOSEST_ULL(vref, full_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		gain = DIV_ROUND_CLOSEST(gain, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		st->gain = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (gain < AD7780_GAIN_MIDPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			gain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		gpiod_set_value(st->gain_gpio, gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (1000*val + val2/1000 < AD7780_FILTER_MIDPOINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		st->odr = ad778x_odr_avail[val];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		gpiod_set_value(st->filter_gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int ad7780_postprocess_sample(struct ad_sigma_delta *sigma_delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				     unsigned int raw_sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct ad7780_state *st = ad_sigma_delta_to_ad7780(sigma_delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	const struct ad7780_chip_info *chip_info = st->chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if ((raw_sample & AD7780_ERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	    ((raw_sample & chip_info->pattern_mask) != chip_info->pattern))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (chip_info->is_ad778x) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		st->gain = ad778x_gain[raw_sample & AD7780_GAIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		st->odr = ad778x_odr_avail[raw_sample & AD7780_FILTER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct ad_sigma_delta_info ad7780_sigma_delta_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.set_mode = ad7780_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.postprocess_sample = ad7780_postprocess_sample,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.has_registers = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.irq_flags = IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define _AD7780_CHANNEL(_bits, _wordsize, _mask_all)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.channel = 0,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		BIT(IIO_CHAN_INFO_OFFSET),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.info_mask_shared_by_all = _mask_all,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.scan_index = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.realbits = (_bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.storagebits = 32,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.shift = (_wordsize) - (_bits),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.endianness = IIO_BE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AD7780_CHANNEL(_bits, _wordsize)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	_AD7780_CHANNEL(_bits, _wordsize, BIT(IIO_CHAN_INFO_SAMP_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AD7170_CHANNEL(_bits, _wordsize)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	_AD7780_CHANNEL(_bits, _wordsize, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct ad7780_chip_info ad7780_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	[ID_AD7170] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.channel = AD7170_CHANNEL(12, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.pattern = AD7170_PATTERN_GOOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.pattern_mask = AD7170_PATTERN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.is_ad778x = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	[ID_AD7171] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.channel = AD7170_CHANNEL(16, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.pattern = AD7170_PATTERN_GOOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.pattern_mask = AD7170_PATTERN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.is_ad778x = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	[ID_AD7780] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.channel = AD7780_CHANNEL(24, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.pattern = AD7780_PATTERN_GOOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.pattern_mask = AD7780_PATTERN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.is_ad778x = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	[ID_AD7781] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.channel = AD7780_CHANNEL(20, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.pattern = AD7780_PATTERN_GOOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.pattern_mask = AD7780_PATTERN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.is_ad778x = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct iio_info ad7780_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.read_raw = ad7780_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.write_raw = ad7780_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int ad7780_init_gpios(struct device *dev, struct ad7780_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	st->powerdown_gpio = devm_gpiod_get_optional(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 						     "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 						     GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (IS_ERR(st->powerdown_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ret = PTR_ERR(st->powerdown_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		dev_err(dev, "Failed to request powerdown GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!st->chip_info->is_ad778x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	st->gain_gpio = devm_gpiod_get_optional(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 						"adi,gain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 						GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (IS_ERR(st->gain_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		ret = PTR_ERR(st->gain_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(dev, "Failed to request gain GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	st->filter_gpio = devm_gpiod_get_optional(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 						  "adi,filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 						  GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (IS_ERR(st->filter_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		ret = PTR_ERR(st->filter_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		dev_err(dev, "Failed to request filter GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int ad7780_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct ad7780_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	st->gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	ad_sd_init(&st->sd, indio_dev, spi, &ad7780_sigma_delta_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	st->chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		&ad7780_chip_info_tbl[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	indio_dev->channels = &st->chip_info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	indio_dev->num_channels = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	indio_dev->info = &ad7780_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	ret = ad7780_init_gpios(&spi->dev, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	st->reg = devm_regulator_get(&spi->dev, "avdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		goto error_cleanup_buffer_and_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) error_cleanup_buffer_and_trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ad7780_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct ad7780_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct spi_device_id ad7780_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	{"ad7170", ID_AD7170},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	{"ad7171", ID_AD7171},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	{"ad7780", ID_AD7780},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	{"ad7781", ID_AD7781},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DEVICE_TABLE(spi, ad7780_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct spi_driver ad7780_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.name	= "ad7780",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.probe		= ad7780_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.remove		= ad7780_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.id_table	= ad7780_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) module_spi_driver(ad7780_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_DESCRIPTION("Analog Devices AD7780 and similar ADCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MODULE_LICENSE("GPL v2");