^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Analog Devices AD7768-1 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2017 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* AD7768 registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD7768_REG_CHIP_TYPE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AD7768_REG_PROD_ID_L 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD7768_REG_PROD_ID_H 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD7768_REG_CHIP_GRADE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD7768_REG_SCRATCH_PAD 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD7768_REG_VENDOR_L 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD7768_REG_VENDOR_H 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD7768_REG_INTERFACE_FORMAT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD7768_REG_POWER_CLOCK 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD7768_REG_ANALOG 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD7768_REG_ANALOG2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD7768_REG_CONVERSION 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD7768_REG_DIGITAL_FILTER 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD7768_REG_SYNC_RESET 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD7768_REG_GPIO_CONTROL 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD7768_REG_GPIO_WRITE 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD7768_REG_GPIO_READ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD7768_REG_OFFSET_HI 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AD7768_REG_OFFSET_MID 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AD7768_REG_OFFSET_LO 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AD7768_REG_GAIN_HI 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AD7768_REG_GAIN_MID 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AD7768_REG_GAIN_LO 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD7768_REG_SPI_DIAG_ENABLE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD7768_REG_ADC_DIAG_ENABLE 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD7768_REG_DIG_DIAG_ENABLE 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AD7768_REG_ADC_DATA 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AD7768_REG_MASTER_STATUS 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD7768_REG_SPI_DIAG_STATUS 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AD7768_REG_ADC_DIAG_STATUS 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD7768_REG_DIG_DIAG_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AD7768_REG_MCLK_COUNTER 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* AD7768_REG_POWER_CLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* AD7768_REG_DIGITAL_FILTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* AD7768_REG_CONVERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AD7768_CONV_MODE_MSK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) enum ad7768_conv_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) AD7768_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AD7768_ONE_SHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) AD7768_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AD7768_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) AD7768_STANDBY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum ad7768_pwrmode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) AD7768_ECO_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AD7768_MED_MODE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) AD7768_FAST_MODE = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum ad7768_mclk_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AD7768_MCLK_DIV_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AD7768_MCLK_DIV_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) AD7768_MCLK_DIV_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) AD7768_MCLK_DIV_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum ad7768_dec_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AD7768_DEC_RATE_32 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AD7768_DEC_RATE_64 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AD7768_DEC_RATE_128 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AD7768_DEC_RATE_256 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AD7768_DEC_RATE_512 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) AD7768_DEC_RATE_1024 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AD7768_DEC_RATE_8 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) AD7768_DEC_RATE_16 = 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ad7768_clk_configuration {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum ad7768_mclk_div mclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum ad7768_dec_rate dec_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum ad7768_pwrmode pwrmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct ad7768_clk_configuration ad7768_clk_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct iio_chan_spec ad7768_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .scan_index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .realbits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .storagebits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct ad7768_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int samp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct gpio_desc *gpio_sync_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __be32 chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) s64 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __be32 d32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 d8[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) shift = 32 - (8 * len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) st->data.d8[0] = AD7768_RD_FLAG_MSK(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = spi_write_then_read(st->spi, st->data.d8, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &st->data.d32, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return (be32_to_cpu(st->data.d32) >> shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int ad7768_spi_reg_write(struct ad7768_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) st->data.d8[0] = AD7768_WR_FLAG_MSK(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) st->data.d8[1] = val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return spi_write(st->spi, st->data.d8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int ad7768_set_mode(struct ad7768_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) enum ad7768_conv_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (regval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) regval &= ~AD7768_CONV_MODE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) regval |= AD7768_CONV_MODE(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int ad7768_scan_direct(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int readval, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reinit_completion(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = wait_for_completion_timeout(&st->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (readval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Any SPI configuration of the AD7768-1 can only be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * performed in continuous conversion mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int ad7768_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (readval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = ad7768_spi_reg_read(st, reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *readval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = ad7768_spi_reg_write(st, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int ad7768_set_dig_fil(struct ad7768_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enum ad7768_dec_rate dec_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mode = AD7768_DIG_FIL_FIL(dec_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mode = AD7768_DIG_FIL_DEC_RATE(dec_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* A sync-in pulse is required every time the filter dec rate changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) gpiod_set_value(st->gpio_sync_in, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) gpiod_set_value(st->gpio_sync_in, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int ad7768_set_freq(struct ad7768_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int diff_new, diff_old, pwr_mode, i, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int res, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) diff_old = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) res = DIV_ROUND_CLOSEST(st->mclk_freq, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Find the closest match for the desired sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) diff_new = abs(res - ad7768_clk_config[i].clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (diff_new < diff_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) diff_old = diff_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Set both the mclk_div and pwrmode with a single write to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * POWER_CLOCK register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ad7768_clk_config[idx].clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static ssize_t ad7768_sampling_freq_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int i, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) freq = DIV_ROUND_CLOSEST(st->mclk_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ad7768_clk_config[i].clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int ad7768_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int scale_uv, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = ad7768_scan_direct(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) scale_uv = regulator_get_voltage(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (scale_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *val = (scale_uv * 2) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *val = st->samp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int ad7768_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ad7768_set_freq(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct attribute *ad7768_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct attribute_group ad7768_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .attrs = ad7768_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct iio_info ad7768_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .attrs = &ad7768_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .read_raw = &ad7768_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .write_raw = &ad7768_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .debugfs_reg_access = &ad7768_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int ad7768_setup(struct ad7768_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Two writes to the SPI_RESET[1:0] bits are required to initiate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * a software reset. The bits must first be set to 11, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * to 10. When the sequence is detected, the reset occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * See the datasheet, page 70.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (IS_ERR(st->gpio_sync_in))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return PTR_ERR(st->gpio_sync_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Set the default sampling frequency to 32000 kSPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ad7768_set_freq(st, 32000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static irqreturn_t ad7768_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = spi_read(st->spi, &st->data.scan.chan, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct iio_dev *indio_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iio_trigger_poll(st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) complete(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * continuous read mode. Subsequent data reads do not require an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * initial 8-bit write to query the ADC_DATA register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct ad7768_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * To exit continuous read mode, perform a single read of the ADC_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * reg (0x2C), which allows further configuration of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .postenable = &ad7768_buffer_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .predisable = &ad7768_buffer_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct iio_trigger_ops ad7768_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .validate_device = iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void ad7768_regulator_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct ad7768_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void ad7768_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ad7768_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clk_disable_unprepare(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int ad7768_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct ad7768_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) st->vref = devm_regulator_get(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (IS_ERR(st->vref))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return PTR_ERR(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = regulator_enable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(&spi->dev, "Failed to enable specified vref supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) st->mclk = devm_clk_get(&spi->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(st->mclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return PTR_ERR(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = clk_prepare_enable(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) st->mclk_freq = clk_get_rate(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) indio_dev->channels = ad7768_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) indio_dev->info = &ad7768_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = ad7768_setup(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(&spi->dev, "AD7768 setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) indio_dev->name, indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (!st->trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) st->trig->ops = &ad7768_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) st->trig->dev.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) iio_trigger_set_drvdata(st->trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = devm_iio_trigger_register(&spi->dev, st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) indio_dev->trig = iio_trigger_get(st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) init_completion(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = devm_request_irq(&spi->dev, spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) &ad7768_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) indio_dev->name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) &ad7768_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &ad7768_buffer_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct spi_device_id ad7768_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { "ad7768-1", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_DEVICE_TABLE(spi, ad7768_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const struct of_device_id ad7768_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { .compatible = "adi,ad7768-1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_DEVICE_TABLE(of, ad7768_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static struct spi_driver ad7768_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .name = "ad7768-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .of_match_table = ad7768_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .probe = ad7768_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .id_table = ad7768_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) module_spi_driver(ad7768_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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