Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD7766/AD7767 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2016 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) struct ad7766_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	unsigned int decimation_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	AD7766_SUPPLY_AVDD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	AD7766_SUPPLY_DVDD = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	AD7766_SUPPLY_VREF = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	AD7766_NUM_SUPPLIES = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct ad7766 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	const struct ad7766_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct gpio_desc *pd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct regulator_bulk_data reg[AD7766_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct spi_transfer xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 * Make the buffer large enough for one 24 bit sample and one 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * aligned 64 bit timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * AD7766 and AD7767 variations are interface compatible, the main difference is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * analog performance. Both parts will use the same ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) enum ad7766_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ID_AD7766,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ID_AD7766_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ID_AD7766_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static irqreturn_t ad7766_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct ad7766 *ad7766 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ret = spi_sync(ad7766->spi, &ad7766->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	iio_push_to_buffers_with_timestamp(indio_dev, ad7766->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int ad7766_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct ad7766 *ad7766 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ret = regulator_bulk_enable(ARRAY_SIZE(ad7766->reg), ad7766->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		dev_err(&ad7766->spi->dev, "Failed to enable supplies: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	ret = clk_prepare_enable(ad7766->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		dev_err(&ad7766->spi->dev, "Failed to enable MCLK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		regulator_bulk_disable(ARRAY_SIZE(ad7766->reg), ad7766->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	gpiod_set_value(ad7766->pd_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int ad7766_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct ad7766 *ad7766 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	gpiod_set_value(ad7766->pd_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * The PD pin is synchronous to the clock, so give it some time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * notice the change before we disable the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	clk_disable_unprepare(ad7766->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	regulator_bulk_disable(ARRAY_SIZE(ad7766->reg), ad7766->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int ad7766_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	const struct iio_chan_spec *chan, int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct ad7766 *ad7766 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct regulator *vref = ad7766->reg[AD7766_SUPPLY_VREF].consumer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		scale_uv = regulator_get_voltage(vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (scale_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			return scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		*val = scale_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		*val = clk_get_rate(ad7766->mclk) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			ad7766->chip_info->decimation_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct iio_chan_spec ad7766_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			.sign = 's',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			.realbits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			.storagebits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			.endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct ad7766_chip_info ad7766_chip_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	[ID_AD7766] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.decimation_factor = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	[ID_AD7766_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.decimation_factor = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	[ID_AD7766_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.decimation_factor = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct iio_buffer_setup_ops ad7766_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.preenable = &ad7766_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.postdisable = &ad7766_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct iio_info ad7766_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.read_raw = &ad7766_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static irqreturn_t ad7766_irq(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	iio_trigger_poll(private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int ad7766_set_trigger_state(struct iio_trigger *trig, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct ad7766 *ad7766 = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		enable_irq(ad7766->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		disable_irq(ad7766->spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct iio_trigger_ops ad7766_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.set_trigger_state = ad7766_set_trigger_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.validate_device = iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int ad7766_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct ad7766 *ad7766;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ad7766));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ad7766 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ad7766->chip_info = &ad7766_chip_info[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ad7766->mclk = devm_clk_get(&spi->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (IS_ERR(ad7766->mclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return PTR_ERR(ad7766->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	ad7766->reg[AD7766_SUPPLY_AVDD].supply = "avdd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ad7766->reg[AD7766_SUPPLY_DVDD].supply = "dvdd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ad7766->reg[AD7766_SUPPLY_VREF].supply = "vref";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(ad7766->reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ad7766->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ad7766->pd_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (IS_ERR(ad7766->pd_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return PTR_ERR(ad7766->pd_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	indio_dev->channels = ad7766_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	indio_dev->num_channels = ARRAY_SIZE(ad7766_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	indio_dev->info = &ad7766_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (spi->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		ad7766->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			indio_dev->name, indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (!ad7766->trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		ad7766->trig->ops = &ad7766_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		ad7766->trig->dev.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		iio_trigger_set_drvdata(ad7766->trig, ad7766);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ret = devm_request_irq(&spi->dev, spi->irq, ad7766_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			IRQF_TRIGGER_FALLING, dev_name(&spi->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			ad7766->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		 * The device generates interrupts as long as it is powered up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		 * Some platforms might not allow the option to power it down so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 * disable the interrupt to avoid extra load on the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		disable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		ret = devm_iio_trigger_register(&spi->dev, ad7766->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ad7766->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* First byte always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ad7766->xfer.rx_buf = &ad7766->data[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	ad7766->xfer.len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	spi_message_init(&ad7766->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	spi_message_add_tail(&ad7766->xfer, &ad7766->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		&iio_pollfunc_store_time, &ad7766_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		&ad7766_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ret = devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct spi_device_id ad7766_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{"ad7766", ID_AD7766},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{"ad7766-1", ID_AD7766_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{"ad7766-2", ID_AD7766_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{"ad7767", ID_AD7766},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{"ad7767-1", ID_AD7766_1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{"ad7767-2", ID_AD7766_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_DEVICE_TABLE(spi, ad7766_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct spi_driver ad7766_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.name	= "ad7766",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.probe		= ad7766_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.id_table	= ad7766_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) module_spi_driver(ad7766_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_DESCRIPTION("Analog Devices AD7766 and AD7767 ADCs driver support");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_LICENSE("GPL v2");