Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD7606 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "ad7606.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MAX_SPI_FREQ_HZ		23500000	/* VDRIVE above 4.75 V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AD7616_CONFIGURATION_REGISTER	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AD7616_OS_MASK			GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AD7616_BURST_MODE		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AD7616_SEQEN_MODE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AD7616_RANGE_CH_A_ADDR_OFF	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AD7616_RANGE_CH_B_ADDR_OFF	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Range of channels from a group are stored in 2 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * For channels from second group(8-15) the order is the same, only with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * an offset of 2 for register address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AD7616_RANGE_CH_ADDR(ch)	((ch) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* The range of the channel is stored in 2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD7616_RANGE_CH_MSK(ch)		(0b11 << (((ch) & 0b11) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD7616_RANGE_CH_MODE(ch, mode)	((mode) << ((((ch) & 0b11)) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AD7606_CONFIGURATION_REGISTER	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AD7606_SINGLE_DOUT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Range for AD7606B channels are stored in registers starting with address 0x3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * Each register stores range for 2 channels(4 bits per channel).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AD7606_RANGE_CH_MSK(ch)		(GENMASK(3, 0) << (4 * ((ch) & 0x1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AD7606_RANGE_CH_MODE(ch, mode)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AD7606_RANGE_CH_ADDR(ch)	(0x03 + ((ch) >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AD7606_OS_MODE			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static const struct iio_chan_spec ad7616_sw_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	IIO_CHAN_SOFT_TIMESTAMP(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	AD7616_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	AD7616_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	AD7616_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	AD7616_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	AD7616_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	AD7616_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	AD7616_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	AD7616_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	AD7616_CHANNEL(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	AD7616_CHANNEL(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	AD7616_CHANNEL(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	AD7616_CHANNEL(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	AD7616_CHANNEL(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	AD7616_CHANNEL(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	AD7616_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	AD7616_CHANNEL(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static const struct iio_chan_spec ad7606b_sw_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	AD7616_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	AD7616_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	AD7616_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	AD7616_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	AD7616_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	AD7616_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	AD7616_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	AD7616_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const unsigned int ad7606B_oversampling_avail[9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	1, 2, 4, 8, 16, 32, 64, 128, 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static u16 ad7616_spi_rd_wr_cmd(int addr, char isWriteOp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * The address of register consist of one w/r bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * 6 bits of address followed by one reserved bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return ((addr & 0x7F) << 1) | ((isWriteOp & 0x1) << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static u16 ad7606B_spi_rd_wr_cmd(int addr, char is_write_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * The address of register consists of one bit which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * specifies a read command placed in bit 6, followed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * 6 bits of address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return (addr & 0x3F) | (((~is_write_op) & 0x1) << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int ad7606_spi_read_block(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				 int count, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned short *data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	__be16 *bdata = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ret = spi_read(spi, buf, count * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		dev_err(&spi->dev, "SPI read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		data[i] = be16_to_cpu(bdata[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct spi_device *spi = to_spi_device(st->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			.tx_buf = &st->d16[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			.cs_change = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			.rx_buf = &st->d16[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	st->d16[0] = cpu_to_be16(st->bops->rd_wr_cmd(addr, 0) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return be16_to_cpu(st->d16[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int ad7606_spi_reg_write(struct ad7606_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct spi_device *spi = to_spi_device(st->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	st->d16[0] = cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				  (val & 0x1FF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return spi_write(spi, &st->d16[0], sizeof(st->d16[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ad7606_spi_write_mask(struct ad7606_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				 unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				 unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				 unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	readval = st->bops->reg_read(st, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (readval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	readval &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	readval |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return st->bops->reg_write(st, addr, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned int ch_addr, mode, ch_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 * Ad7616 has 16 channels divided in group A and group B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * The range of channels from A are stored in registers with address 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * while channels from B are stored in register with address 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * The last bit from channels determines if it is from group A or B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 * because the order of channels in iio is 0A, 0B, 1A, 1B...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ch_index = ch >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ch_addr = AD7616_RANGE_CH_ADDR(ch_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if ((ch & 0x1) == 0) /* channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		ch_addr += AD7616_RANGE_CH_A_ADDR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	else	/* channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		ch_addr += AD7616_RANGE_CH_B_ADDR_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				     mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				     AD7616_OS_MASK, val << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return ad7606_spi_write_mask(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				     AD7606_RANGE_CH_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				     AD7606_RANGE_CH_MSK(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				     AD7606_RANGE_CH_MODE(ch, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return ad7606_spi_reg_write(st, AD7606_OS_MODE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ad7616_sw_mode_config(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * Scale can be configured individually for each channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * in software mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	indio_dev->channels = ad7616_sw_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	st->write_scale = ad7616_write_scale_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	st->write_os = &ad7616_write_os_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Activate Burst mode and SEQEN MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return st->bops->write_mask(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			      AD7616_CONFIGURATION_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			      AD7616_BURST_MODE | AD7616_SEQEN_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			      AD7616_BURST_MODE | AD7616_SEQEN_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int ad7606B_sw_mode_config(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	unsigned long os[3] = {1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * Software mode is enabled when all three oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * pins are set to high. If oversampling gpios are defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * in the device tree, then they need to be set to high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * otherwise, they must be hardwired to VDD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (st->gpio_os) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		gpiod_set_array_value(ARRAY_SIZE(os),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				      st->gpio_os->desc, st->gpio_os->info, os);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* OS of 128 and 256 are available only in software mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	st->oversampling_avail = ad7606B_oversampling_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	st->num_os_ratios = ARRAY_SIZE(ad7606B_oversampling_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	st->write_scale = ad7606_write_scale_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	st->write_os = &ad7606_write_os_sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/* Configure device spi to output on a single channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	st->bops->reg_write(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			    AD7606_CONFIGURATION_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			    AD7606_SINGLE_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * Scale can be configured individually for each channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * in software mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	indio_dev->channels = ad7606b_sw_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct ad7606_bus_ops ad7606_spi_bops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.read_block = ad7606_spi_read_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct ad7606_bus_ops ad7616_spi_bops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.read_block = ad7606_spi_read_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.reg_read = ad7606_spi_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.reg_write = ad7606_spi_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.write_mask = ad7606_spi_write_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.rd_wr_cmd = ad7616_spi_rd_wr_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.sw_mode_config = ad7616_sw_mode_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct ad7606_bus_ops ad7606B_spi_bops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.read_block = ad7606_spi_read_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.reg_read = ad7606_spi_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.reg_write = ad7606_spi_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.write_mask = ad7606_spi_write_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.rd_wr_cmd = ad7606B_spi_rd_wr_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.sw_mode_config = ad7606B_sw_mode_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ad7606_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	const struct spi_device_id *id = spi_get_device_id(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	const struct ad7606_bus_ops *bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	switch (id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	case ID_AD7616:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		bops = &ad7616_spi_bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	case ID_AD7606B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		bops = &ad7606B_spi_bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		bops = &ad7606_spi_bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return ad7606_probe(&spi->dev, spi->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			    id->name, id->driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			    bops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct spi_device_id ad7606_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ "ad7605-4", ID_AD7605_4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ "ad7606-4", ID_AD7606_4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ "ad7606-6", ID_AD7606_6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{ "ad7606-8", ID_AD7606_8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ "ad7606b",  ID_AD7606B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ "ad7616",   ID_AD7616 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DEVICE_TABLE(spi, ad7606_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct of_device_id ad7606_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	{ .compatible = "adi,ad7605-4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{ .compatible = "adi,ad7606-4" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{ .compatible = "adi,ad7606-6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	{ .compatible = "adi,ad7606-8" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{ .compatible = "adi,ad7606b" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	{ .compatible = "adi,ad7616" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_DEVICE_TABLE(of, ad7606_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct spi_driver ad7606_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.name = "ad7606",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.of_match_table = ad7606_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.pm = AD7606_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.probe = ad7606_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.id_table = ad7606_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) module_spi_driver(ad7606_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_LICENSE("GPL v2");