^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7606 ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef IIO_ADC_AD7606_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IIO_ADC_AD7606_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .channel = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .address = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .info_mask_separate = mask_sep, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .info_mask_shared_by_type = mask_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .info_mask_shared_by_all = mask_all, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .scan_index = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .realbits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AD7605_CHANNEL(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) BIT(IIO_CHAN_INFO_SCALE), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD7606_CHANNEL(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD7616_CHANNEL(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * struct ad7606_chip_info - chip specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @channels: channel specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @num_channels: number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @oversampling_avail pointer to the array which stores the available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * oversampling ratios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @oversampling_num number of elements stored in oversampling_avail array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @os_req_reset some devices require a reset to update oversampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @init_delay_ms required delay in miliseconds for initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * after a restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ad7606_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const unsigned int *oversampling_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int oversampling_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool os_req_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long init_delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * struct ad7606_state - driver instance specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @dev pointer to kernel device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @chip_info entry in the table of chips that describes this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @reg regulator info for the the power supply of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @bops bus operations (SPI or parallel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @range voltage range selection, selects which scale to apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @oversampling oversampling selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @base_address address from where to read data in parallel operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @sw_mode_en software mode enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @scale_avail pointer to the array which stores the available scales
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @num_scales number of elements stored in the scale_avail array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @oversampling_avail pointer to the array which stores the available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * oversampling ratios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @num_os_ratios number of elements stored in oversampling_avail array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @write_scale pointer to the function which writes the scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @write_os pointer to the function which writes the os
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @lock protect sensor state from concurrent accesses to GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @gpio_convst GPIO descriptor for conversion start signal (CONVST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @gpio_reset GPIO descriptor for device hard-reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @gpio_range GPIO descriptor for range selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @gpio_standby GPIO descriptor for stand-by signal (STBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * controls power-down mode of device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @gpio_frstdata GPIO descriptor for reading from device when data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * is being read on the first channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @gpio_os GPIO descriptors to control oversampling on the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @complete completion to indicate end of conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @trig The IIO trigger associated with the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @data buffer for reading data from the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @d16 be16 buffer for reading data from the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct ad7606_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct ad7606_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct ad7606_bus_ops *bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int range[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int oversampling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool sw_mode_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const unsigned int *scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int num_scales;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const unsigned int *oversampling_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int num_os_ratios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int (*write_scale)(struct iio_dev *indio_dev, int ch, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int (*write_os)(struct iio_dev *indio_dev, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mutex lock; /* protect sensor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct gpio_desc *gpio_convst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct gpio_desc *gpio_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct gpio_desc *gpio_standby;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct gpio_desc *gpio_frstdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gpio_descs *gpio_os;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * 16 * 16-bit samples + 64-bit timestamp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned short data[20] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __be16 d16[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * struct ad7606_bus_ops - driver bus operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @read_block function pointer for reading blocks of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @sw_mode_config: pointer to a function which configured the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * for software mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @reg_read function pointer for reading spi register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @reg_write function pointer for writing spi register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @write_mask function pointer for write spi register with mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @rd_wr_cmd pointer to the function which calculates the spi address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ad7606_bus_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* more methods added in future? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int (*read_block)(struct device *dev, int num, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*sw_mode_config)(struct iio_dev *indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int (*reg_read)(struct ad7606_state *st, unsigned int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int (*reg_write)(struct ad7606_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int (*write_mask)(struct ad7606_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 (*rd_wr_cmd)(int addr, char isWriteOp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *name, unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct ad7606_bus_ops *bops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) enum ad7606_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ID_AD7605_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ID_AD7606_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ID_AD7606_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ID_AD7606_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ID_AD7606B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ID_AD7616,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) extern const struct dev_pm_ops ad7606_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AD7606_PM_OPS (&ad7606_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AD7606_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif /* IIO_ADC_AD7606_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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