^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7606 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/util_macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "ad7606.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Scales are computed as 5000/32768 and 10000/32768 respectively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * so that when applied to the raw values they provide mV values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const unsigned int ad7606_scale_avail[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 152588, 305176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const unsigned int ad7616_sw_scale_avail[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 76293, 152588, 305176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const unsigned int ad7606_oversampling_avail[7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 1, 2, 4, 8, 16, 32, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const unsigned int ad7616_oversampling_avail[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1, 2, 4, 8, 16, 32, 64, 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int ad7606_reset(struct ad7606_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (st->gpio_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) gpiod_set_value(st->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ndelay(100); /* t_reset >= 100ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) gpiod_set_value(st->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int ad7606_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (readval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = st->bops->reg_read(st, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *readval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = st->bops->reg_write(st, reg, writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int ad7606_read_samples(struct ad7606_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int num = st->chip_info->num_channels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 *data = st->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * The frstdata signal is set to high while and after reading the sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * of the first channel and low for all other channels. This can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * to check that the incoming data is correctly aligned. During normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * operation the data should never become unaligned, but some glitch or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * electrostatic discharge might cause an extra read or clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Monitoring the frstdata signal allows to recover from such failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * situations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (st->gpio_frstdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = st->bops->read_block(st->dev, 1, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!gpiod_get_value(st->gpio_frstdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ad7606_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return st->bops->read_block(st->dev, num, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static irqreturn_t ad7606_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = ad7606_read_samples(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) iio_push_to_buffers_with_timestamp(indio_dev, st->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* The rising edge of the CONVST signal starts a new conversion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) gpiod_set_value(st->gpio_convst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) gpiod_set_value(st->gpio_convst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = wait_for_completion_timeout(&st->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = ad7606_read_samples(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = st->data[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) gpiod_set_value(st->gpio_convst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int ad7606_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret, ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = ad7606_scan_direct(indio_dev, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *val = (short)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (st->sw_mode_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ch = chan->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *val2 = st->scale_avail[st->range[ch]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *val = st->oversampling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static ssize_t ad7606_show_avail(char *buf, const unsigned int *vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int n, bool micros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) len += scnprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) micros ? "0.%06u " : "%u ", vals[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static ssize_t in_voltage_scale_available_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ad7606_show_avail(buf, st->scale_avail, st->num_scales, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) gpiod_set_value(st->gpio_range, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DECLARE_BITMAP(values, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) values[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) gpiod_set_array_value(ARRAY_SIZE(values), st->gpio_os->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) st->gpio_os->info, values);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* AD7616 requires a reset to update value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (st->chip_info->os_req_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ad7606_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int ad7606_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int i, ret, ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) i = find_closest(val2, st->scale_avail, st->num_scales);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (st->sw_mode_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ch = chan->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = st->write_scale(indio_dev, ch, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) st->range[ch] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) i = find_closest(val, st->oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) st->num_os_ratios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = st->write_os(indio_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) st->oversampling = st->oversampling_avail[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static ssize_t ad7606_oversampling_ratio_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ad7606_show_avail(buf, st->oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) st->num_os_ratios, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static IIO_DEVICE_ATTR(oversampling_ratio_available, 0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ad7606_oversampling_ratio_avail, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct attribute *ad7606_attributes_os_and_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct attribute_group ad7606_attribute_group_os_and_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .attrs = ad7606_attributes_os_and_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct attribute *ad7606_attributes_os[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) &iio_dev_attr_oversampling_ratio_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct attribute_group ad7606_attribute_group_os = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .attrs = ad7606_attributes_os,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct attribute *ad7606_attributes_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct attribute_group ad7606_attribute_group_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .attrs = ad7606_attributes_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct iio_chan_spec ad7605_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) AD7605_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) AD7605_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) AD7605_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AD7605_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct iio_chan_spec ad7606_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) AD7606_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AD7606_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) AD7606_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) AD7606_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AD7606_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AD7606_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AD7606_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) AD7606_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * The current assumption that this driver makes for AD7616, is that it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * working in Hardware Mode with Serial, Burst and Sequencer modes activated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * To activate them, following pins must be pulled high:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * -SER/PAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * -SEQEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * And following pins must be pulled low:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * -WR/BURST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * -DB4/SER1W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const struct iio_chan_spec ad7616_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) IIO_CHAN_SOFT_TIMESTAMP(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) AD7606_CHANNEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) AD7606_CHANNEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) AD7606_CHANNEL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) AD7606_CHANNEL(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) AD7606_CHANNEL(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) AD7606_CHANNEL(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) AD7606_CHANNEL(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) AD7606_CHANNEL(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) AD7606_CHANNEL(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) AD7606_CHANNEL(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) AD7606_CHANNEL(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) AD7606_CHANNEL(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) AD7606_CHANNEL(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) AD7606_CHANNEL(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) AD7606_CHANNEL(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AD7606_CHANNEL(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct ad7606_chip_info ad7606_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* More devices added in future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [ID_AD7605_4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .channels = ad7605_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [ID_AD7606_8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .channels = ad7606_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .num_channels = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .oversampling_avail = ad7606_oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [ID_AD7606_6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .channels = ad7606_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .num_channels = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .oversampling_avail = ad7606_oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [ID_AD7606_4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .channels = ad7606_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .num_channels = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .oversampling_avail = ad7606_oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [ID_AD7606B] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .channels = ad7606_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .num_channels = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .oversampling_avail = ad7606_oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [ID_AD7616] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .channels = ad7616_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .num_channels = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .oversampling_avail = ad7616_oversampling_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .os_req_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .init_delay_ms = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int ad7606_request_gpios(struct ad7606_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct device *dev = st->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) st->gpio_convst = devm_gpiod_get(dev, "adi,conversion-start",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (IS_ERR(st->gpio_convst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return PTR_ERR(st->gpio_convst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (IS_ERR(st->gpio_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return PTR_ERR(st->gpio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) st->gpio_range = devm_gpiod_get_optional(dev, "adi,range",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (IS_ERR(st->gpio_range))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return PTR_ERR(st->gpio_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) st->gpio_standby = devm_gpiod_get_optional(dev, "standby",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (IS_ERR(st->gpio_standby))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return PTR_ERR(st->gpio_standby);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (IS_ERR(st->gpio_frstdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return PTR_ERR(st->gpio_frstdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!st->chip_info->oversampling_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) st->gpio_os = devm_gpiod_get_array_optional(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "adi,oversampling-ratio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return PTR_ERR_OR_ZERO(st->gpio_os);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * The BUSY signal indicates when conversions are in progress, so when a rising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * edge of CONVST is applied, BUSY goes logic high and transitions low at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * end of the entire conversion process. The falling edge of the BUSY signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * triggers this interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static irqreturn_t ad7606_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct iio_dev *indio_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (iio_buffer_enabled(indio_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) gpiod_set_value(st->gpio_convst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) iio_trigger_poll_chained(st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) complete(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int ad7606_validate_trigger(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (st->trig != trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int ad7606_buffer_postenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gpiod_set_value(st->gpio_convst, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int ad7606_buffer_predisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) gpiod_set_value(st->gpio_convst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct iio_buffer_setup_ops ad7606_buffer_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .postenable = &ad7606_buffer_postenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .predisable = &ad7606_buffer_predisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct iio_info ad7606_info_no_os_or_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .read_raw = &ad7606_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .validate_trigger = &ad7606_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct iio_info ad7606_info_os_and_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .read_raw = &ad7606_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .write_raw = &ad7606_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .attrs = &ad7606_attribute_group_os_and_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .validate_trigger = &ad7606_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct iio_info ad7606_info_os_range_and_debug = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .read_raw = &ad7606_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .write_raw = &ad7606_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .debugfs_reg_access = &ad7606_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .attrs = &ad7606_attribute_group_os_and_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .validate_trigger = &ad7606_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct iio_info ad7606_info_os = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .read_raw = &ad7606_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .write_raw = &ad7606_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .attrs = &ad7606_attribute_group_os,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .validate_trigger = &ad7606_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct iio_info ad7606_info_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .read_raw = &ad7606_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .write_raw = &ad7606_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .attrs = &ad7606_attribute_group_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .validate_trigger = &ad7606_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct iio_trigger_ops ad7606_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .validate_device = iio_trigger_validate_own_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void ad7606_regulator_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct ad7606_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) const char *name, unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) const struct ad7606_bus_ops *bops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct ad7606_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_set_drvdata(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) st->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) st->bops = bops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) st->base_address = base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* tied to logic low, analog input range is +/- 5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) st->range[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) st->oversampling = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) st->scale_avail = ad7606_scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) st->num_scales = ARRAY_SIZE(ad7606_scale_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) st->reg = devm_regulator_get(dev, "avcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_err(dev, "Failed to enable specified AVcc supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = devm_add_action_or_reset(dev, ad7606_regulator_disable, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) st->chip_info = &ad7606_chip_info_tbl[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (st->chip_info->oversampling_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) st->oversampling_avail = st->chip_info->oversampling_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) st->num_os_ratios = st->chip_info->oversampling_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = ad7606_request_gpios(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (st->gpio_os) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (st->gpio_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) indio_dev->info = &ad7606_info_os_and_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) indio_dev->info = &ad7606_info_os;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (st->gpio_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) indio_dev->info = &ad7606_info_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) indio_dev->info = &ad7606_info_no_os_or_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) indio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) indio_dev->channels = st->chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) indio_dev->num_channels = st->chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) init_completion(&st->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = ad7606_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* AD7616 requires al least 15ms to reconfigure after a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (st->chip_info->init_delay_ms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (msleep_interruptible(st->chip_info->init_delay_ms))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) st->write_scale = ad7606_write_scale_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) st->write_os = ad7606_write_os_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (st->bops->sw_mode_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) st->sw_mode_en = device_property_present(st->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "adi,sw-mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (st->sw_mode_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Scale of 0.076293 is only available in sw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) st->scale_avail = ad7616_sw_scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) st->num_scales = ARRAY_SIZE(ad7616_sw_scale_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* After reset, in software mode, ±10 V is set by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) memset32(st->range, 2, ARRAY_SIZE(st->range));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) indio_dev->info = &ad7606_info_os_range_and_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = st->bops->sw_mode_config(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) indio_dev->name, indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!st->trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) st->trig->ops = &ad7606_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) st->trig->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) iio_trigger_set_drvdata(st->trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = devm_iio_trigger_register(dev, st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) indio_dev->trig = iio_trigger_get(st->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = devm_request_threaded_irq(dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) &ad7606_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) name, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) &ad7606_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) &ad7606_buffer_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return devm_iio_device_register(dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) EXPORT_SYMBOL_GPL(ad7606_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int ad7606_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (st->gpio_standby) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) gpiod_set_value(st->gpio_range, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) gpiod_set_value(st->gpio_standby, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int ad7606_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct iio_dev *indio_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct ad7606_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (st->gpio_standby) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) gpiod_set_value(st->gpio_range, st->range[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) gpiod_set_value(st->gpio_standby, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ad7606_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) EXPORT_SYMBOL_GPL(ad7606_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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