Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2010 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct ad7476_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct ad7476_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned int			int_vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct iio_chan_spec		channel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	/* channels used when convst gpio is defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct iio_chan_spec		convst_channel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	void (*reset)(struct ad7476_state *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct ad7476_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct spi_device		*spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	const struct ad7476_chip_info	*chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct regulator		*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct gpio_desc		*convst_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct spi_transfer		xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct spi_message		msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * Make the buffer large enough for one 16 bit sample and one 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 * aligned 64 bit timestamp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) enum ad7476_supported_device_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	ID_AD7091R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	ID_AD7276,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	ID_AD7277,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ID_AD7278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ID_AD7466,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ID_AD7467,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	ID_AD7468,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ID_AD7495,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ID_AD7940,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ID_ADC081S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ID_ADC101S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ID_ADC121S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	ID_ADS7866,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	ID_ADS7867,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	ID_ADS7868,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static void ad7091_convst(struct ad7476_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (!st->convst_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	gpiod_set_value(st->convst_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	udelay(1); /* CONVST pulse width: 10 ns min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	gpiod_set_value(st->convst_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	udelay(1); /* Conversion time: 650 ns max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static irqreturn_t ad7476_trigger_handler(int irq, void  *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct ad7476_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int b_sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ad7091_convst(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	b_sent = spi_sync(st->spi, &st->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (b_sent < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		iio_get_time_ns(indio_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void ad7091_reset(struct ad7476_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Any transfers with 8 scl cycles will reset the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	spi_read(st->spi, st->data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int ad7476_scan_direct(struct ad7476_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	ad7091_convst(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	ret = spi_sync(st->spi, &st->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return be16_to_cpup((__be16 *)st->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int ad7476_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			   int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			   int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			   long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct ad7476_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		ret = ad7476_scan_direct(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		*val = (ret >> st->chip_info->channel[0].scan_type.shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (!st->chip_info->int_vref_uv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			scale_uv = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			if (scale_uv < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				return scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			scale_uv = st->chip_info->int_vref_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		*val = scale_uv / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define _AD7476_CHAN(bits, _shift, _info_mask_sep)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.type = IIO_VOLTAGE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.indexed = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.info_mask_separate = _info_mask_sep,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.sign = 'u',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.realbits = (bits),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.storagebits = 16,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.shift = (_shift),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.endianness = IIO_BE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		BIT(IIO_CHAN_INFO_RAW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		BIT(IIO_CHAN_INFO_RAW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		BIT(IIO_CHAN_INFO_RAW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		BIT(IIO_CHAN_INFO_RAW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		BIT(IIO_CHAN_INFO_RAW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	[ID_AD7091R] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.channel[0] = AD7091R_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.convst_channel[0] = AD7091R_CONVST_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.reset = ad7091_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	[ID_AD7276] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.channel[0] = AD7940_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	[ID_AD7277] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.channel[0] = AD7940_CHAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	[ID_AD7278] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.channel[0] = AD7940_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	[ID_AD7466] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.channel[0] = AD7476_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	[ID_AD7467] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.channel[0] = AD7476_CHAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	[ID_AD7468] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.channel[0] = AD7476_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	[ID_AD7495] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.channel[0] = AD7476_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.int_vref_uv = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	[ID_AD7940] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.channel[0] = AD7940_CHAN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	[ID_ADC081S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.channel[0] = ADC081S_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	[ID_ADC101S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.channel[0] = ADC081S_CHAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	[ID_ADC121S] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.channel[0] = ADC081S_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	[ID_ADS7866] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		.channel[0] = ADS786X_CHAN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	[ID_ADS7867] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.channel[0] = ADS786X_CHAN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	[ID_ADS7868] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.channel[0] = ADS786X_CHAN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct iio_info ad7476_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.read_raw = &ad7476_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void ad7476_reg_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct ad7476_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int ad7476_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct ad7476_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	st->chip_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		&ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	st->reg = devm_regulator_get(&spi->dev, "vcc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				       st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 						  "adi,conversion-start",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 						  GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (IS_ERR(st->convst_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return PTR_ERR(st->convst_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	indio_dev->channels = st->chip_info->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	indio_dev->num_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	indio_dev->info = &ad7476_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (st->convst_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		indio_dev->channels = st->chip_info->convst_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	/* Setup default message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	st->xfer.rx_buf = &st->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	spi_message_init(&st->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	spi_message_add_tail(&st->xfer, &st->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					      &ad7476_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (st->chip_info->reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		st->chip_info->reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct spi_device_id ad7476_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{"ad7091", ID_AD7091R},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{"ad7091r", ID_AD7091R},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{"ad7273", ID_AD7277},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{"ad7274", ID_AD7276},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{"ad7276", ID_AD7276},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{"ad7277", ID_AD7277},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{"ad7278", ID_AD7278},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{"ad7466", ID_AD7466},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	{"ad7467", ID_AD7467},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{"ad7468", ID_AD7468},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	{"ad7475", ID_AD7466},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	{"ad7476", ID_AD7466},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{"ad7476a", ID_AD7466},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	{"ad7477", ID_AD7467},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{"ad7477a", ID_AD7467},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	{"ad7478", ID_AD7468},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	{"ad7478a", ID_AD7468},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	{"ad7495", ID_AD7495},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{"ad7910", ID_AD7467},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	{"ad7920", ID_AD7466},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	{"ad7940", ID_AD7940},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	{"adc081s", ID_ADC081S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{"adc101s", ID_ADC101S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	{"adc121s", ID_ADC121S},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	{"ads7866", ID_ADS7866},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{"ads7867", ID_ADS7867},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{"ads7868", ID_ADS7868},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_DEVICE_TABLE(spi, ad7476_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct spi_driver ad7476_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.name	= "ad7476",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.probe		= ad7476_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.id_table	= ad7476_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) module_spi_driver(ad7476_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MODULE_LICENSE("GPL v2");