Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Analog Devices AD7292 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2019 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ADI_VENDOR_ID 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* AD7292 registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AD7292_REG_VENDOR_ID		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AD7292_REG_CONF_BANK		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AD7292_REG_CONV_COMM		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AD7292_REG_ADC_CH(x)		(0x10 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* AD7292 configuration bank subregisters definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AD7292_BANK_REG_VIN_RNG0	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AD7292_BANK_REG_VIN_RNG1	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD7292_BANK_REG_SAMP_MODE	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AD7292_RD_FLAG_MSK(x)		(BIT(7) | ((x) & 0x3F))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* AD7292_REG_ADC_CONVERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD7292_ADC_DATA_MASK		GENMASK(15, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AD7292_ADC_DATA(x)		FIELD_GET(AD7292_ADC_DATA_MASK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* AD7292_CHANNEL_SAMPLING_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AD7292_CH_SAMP_MODE(reg, ch)	(((reg) >> 8) & BIT(ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* AD7292_CHANNEL_VIN_RANGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AD7292_CH_VIN_RANGE(reg, ch)	((reg) & BIT(ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AD7292_VOLTAGE_CHAN(_chan)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.type = IIO_VOLTAGE,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			      BIT(IIO_CHAN_INFO_SCALE),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.indexed = 1,							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.channel = _chan,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static const struct iio_chan_spec ad7292_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	AD7292_VOLTAGE_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	AD7292_VOLTAGE_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	AD7292_VOLTAGE_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	AD7292_VOLTAGE_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	AD7292_VOLTAGE_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	AD7292_VOLTAGE_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	AD7292_VOLTAGE_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	AD7292_VOLTAGE_CHAN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct iio_chan_spec ad7292_channels_diff[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.differential = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.channel2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	AD7292_VOLTAGE_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	AD7292_VOLTAGE_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	AD7292_VOLTAGE_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	AD7292_VOLTAGE_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	AD7292_VOLTAGE_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	AD7292_VOLTAGE_CHAN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) struct ad7292_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	unsigned short vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	__be16 d16 ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 d8[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static int ad7292_spi_reg_read(struct ad7292_state *st, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	st->d8[0] = AD7292_RD_FLAG_MSK(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	ret = spi_write_then_read(st->spi, st->d8, 1, &st->d16, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return be16_to_cpu(st->d16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int ad7292_spi_subreg_read(struct ad7292_state *st, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				  unsigned int sub_addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned int shift = 16 - (8 * len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	st->d8[0] = AD7292_RD_FLAG_MSK(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	st->d8[1] = sub_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ret = spi_write_then_read(st->spi, st->d8, 2, &st->d16, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return (be16_to_cpu(st->d16) >> shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int ad7292_single_conversion(struct ad7292_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				    unsigned int chan_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct spi_transfer t[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			.tx_buf = &st->d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			.len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			.delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				.value = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				.unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			.rx_buf = &st->d16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			.len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	st->d8[0] = chan_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	st->d8[1] = AD7292_RD_FLAG_MSK(AD7292_REG_CONV_COMM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return be16_to_cpu(st->d16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int ad7292_vin_range_multiplier(struct ad7292_state *st, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int samp_mode, range0, range1, factor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * Every AD7292 ADC channel may have its input range adjusted according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * to the settings at the ADC sampling mode and VIN range subregisters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * For a given channel, the minimum input range is equal to Vref, and it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * may be increased by a multiplier factor of 2 or 4 according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * following rule:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * If channel is being sampled with respect to AGND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 *	factor = 4 if VIN range0 and VIN range1 equal 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 *	factor = 2 if only one of VIN ranges equal 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 *	factor = 1 if both VIN range0 and VIN range1 equal 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * If channel is being sampled with respect to AVDD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 *	factor = 4 if VIN range0 and VIN range1 equal 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 *	Behavior is undefined if any of VIN range doesn't equal 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	samp_mode = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 					   AD7292_BANK_REG_SAMP_MODE, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (samp_mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return samp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	range0 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 					AD7292_BANK_REG_VIN_RNG0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (range0 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return range0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	range1 = ad7292_spi_subreg_read(st, AD7292_REG_CONF_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					AD7292_BANK_REG_VIN_RNG1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (range1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return range1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (AD7292_CH_SAMP_MODE(samp_mode, channel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		/* Sampling with respect to AGND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (!AD7292_CH_VIN_RANGE(range0, channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			factor *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (!AD7292_CH_VIN_RANGE(range1, channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			factor *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* Sampling with respect to AVDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (AD7292_CH_VIN_RANGE(range0, channel) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		    AD7292_CH_VIN_RANGE(range1, channel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		factor = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int ad7292_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			   const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			   int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct ad7292_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned int ch_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		ch_addr = AD7292_REG_ADC_CH(chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		ret = ad7292_single_conversion(st, ch_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		*val = AD7292_ADC_DATA(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		 * To convert a raw value to standard units, the IIO defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		 * this formula: Scaled value = (raw + offset) * scale.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		 * For the scale to be a correct multiplier for (raw + offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		 * it must be calculated as the input range divided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		 * number of possible distinct input values. Given the ADC data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		 * is 10 bit long, it may assume 2^10 distinct values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		 * Hence, scale = range / 2^10. The IIO_VAL_FRACTIONAL_LOG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		 * return type indicates to the IIO API to divide *val by 2 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		 * the power of *val2 when returning from read_raw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		ret = ad7292_vin_range_multiplier(st, chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		*val = st->vref_mv * ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		*val2 = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct iio_info ad7292_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.read_raw = ad7292_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void ad7292_regulator_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct ad7292_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int ad7292_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct ad7292_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	bool diff_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = ad7292_spi_reg_read(st, AD7292_REG_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret != ADI_VENDOR_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		dev_err(&spi->dev, "Wrong vendor id 0x%x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	st->reg = devm_regulator_get_optional(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!IS_ERR(st->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				"Failed to enable external vref supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = devm_add_action_or_reset(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					       ad7292_regulator_disable, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		ret = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		st->vref_mv = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		/* Use the internal voltage reference. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		st->vref_mv = 1250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	indio_dev->info = &ad7292_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	for_each_available_child_of_node(spi->dev.of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		diff_channels = of_property_read_bool(child, "diff-channels");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if (diff_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (diff_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		indio_dev->num_channels = ARRAY_SIZE(ad7292_channels_diff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		indio_dev->channels = ad7292_channels_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		indio_dev->num_channels = ARRAY_SIZE(ad7292_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		indio_dev->channels = ad7292_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	return devm_iio_device_register(&spi->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct spi_device_id ad7292_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ "ad7292", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_DEVICE_TABLE(spi, ad7292_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct of_device_id ad7292_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ .compatible = "adi,ad7292" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_DEVICE_TABLE(of, ad7292_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct spi_driver ad7292_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.name = "ad7292",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.of_match_table = ad7292_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.probe = ad7292_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.id_table = ad7292_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) module_spi_driver(ad7292_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt1@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DESCRIPTION("Analog Devices AD7292 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_LICENSE("GPL v2");