^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7291 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010-2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Simplified handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * If no events enabled - single polled channel read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * If event enabled direct reads disable unless channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * is in the read mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The noise-delayed bit as per datasheet suggestion is always enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * AD7291 registers definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD7291_COMMAND 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD7291_VOLTAGE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD7291_T_SENSE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD7291_T_AVERAGE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AD7291_DATA_HIGH(x) ((x) * 3 + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD7291_DATA_LOW(x) ((x) * 3 + 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AD7291_HYST(x) ((x) * 3 + 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD7291_VOLTAGE_ALERT_STATUS 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD7291_T_ALERT_STATUS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD7291_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD7291_VOLTAGE_LIMIT_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * AD7291 command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD7291_AUTOCYCLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD7291_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD7291_ALERT_CLEAR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AD7291_ALERT_POLARITY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AD7291_EXT_REF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AD7291_NOISE_DELAY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AD7291_T_SENSE_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD7291_VOLTAGE_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AD7291_VOLTAGE_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * AD7291 value masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD7291_VALUE_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * AD7291 alert register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD7291_T_LOW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD7291_T_HIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD7291_T_AVG_LOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AD7291_T_AVG_HIGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AD7291_V_LOW(x) BIT((x) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AD7291_V_HIGH(x) BIT((x) * 2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct ad7291_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 c_mask; /* Active voltage channels for events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mutex state_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int ad7291_i2c_read(struct ad7291_chip_info *chip, u8 reg, u16 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_client *client = chip->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = i2c_smbus_read_word_swapped(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_err(&client->dev, "I2C read error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *data = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int ad7291_i2c_write(struct ad7291_chip_info *chip, u8 reg, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return i2c_smbus_write_word_swapped(chip->client, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static irqreturn_t ad7291_event_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ad7291_chip_info *chip = iio_priv(private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 t_status, v_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) s64 timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ad7291_i2c_read(chip, AD7291_T_ALERT_STATUS, &t_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ad7291_i2c_read(chip, AD7291_VOLTAGE_ALERT_STATUS, &v_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!(t_status || v_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) command = chip->command | AD7291_ALERT_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ad7291_i2c_write(chip, AD7291_COMMAND, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) command = chip->command & ~AD7291_ALERT_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ad7291_i2c_write(chip, AD7291_COMMAND, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* For now treat t_sense and t_sense_average the same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if ((t_status & AD7291_T_LOW) || (t_status & AD7291_T_AVG_LOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) IIO_UNMOD_EVENT_CODE(IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if ((t_status & AD7291_T_HIGH) || (t_status & AD7291_T_AVG_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) IIO_UNMOD_EVENT_CODE(IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (i = 0; i < AD7291_VOLTAGE_LIMIT_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (v_status & AD7291_V_LOW(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (v_status & AD7291_V_HIGH(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static unsigned int ad7291_threshold_reg(const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum iio_event_info info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) offset = chan->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) offset = AD7291_VOLTAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (dir == IIO_EV_DIR_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return AD7291_DATA_HIGH(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return AD7291_DATA_LOW(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case IIO_EV_INFO_HYSTERESIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return AD7291_HYST(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int ad7291_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ad7291_chip_info *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 uval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = ad7291_i2c_read(chip, ad7291_threshold_reg(chan, dir, info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) &uval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (info == IIO_EV_INFO_HYSTERESIS || chan->type == IIO_VOLTAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *val = uval & AD7291_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *val = sign_extend32(uval, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int ad7291_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct ad7291_chip_info *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (info == IIO_EV_INFO_HYSTERESIS || chan->type == IIO_VOLTAGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (val > AD7291_VALUE_MASK || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (val > 2047 || val < -2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ad7291_i2c_write(chip, ad7291_threshold_reg(chan, dir, info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ad7291_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct ad7291_chip_info *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * To be enabled the channel must simply be on. If any are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * we are in continuous sampling mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return !!(chip->c_mask & BIT(15 - chan->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* always on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int ad7291_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct ad7291_chip_info *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u16 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mutex_lock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) regval = chip->command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * To be enabled the channel must simply be on. If any are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * use continuous sampling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Possible to disable temp as well but that makes single read tricky.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mask = BIT(15 - chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if ((!state) && (chip->c_mask & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) chip->c_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else if (state && (!(chip->c_mask & mask)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) chip->c_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regval &= ~AD7291_AUTOCYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) regval |= chip->c_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (chip->c_mask) /* Enable autocycle? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) regval |= AD7291_AUTOCYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) chip->command = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mutex_unlock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int ad7291_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct ad7291_chip_info *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mutex_lock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* If in autocycle mode drop through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (chip->command & AD7291_AUTOCYCLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mutex_unlock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Enable this channel alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regval = chip->command & (~AD7291_VOLTAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) regval |= BIT(15 - chan->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mutex_unlock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Read voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = i2c_smbus_read_word_swapped(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) AD7291_VOLTAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mutex_unlock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *val = ret & AD7291_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_unlock(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Assumes tsense bit of command register always set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = i2c_smbus_read_word_swapped(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) AD7291_T_SENSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *val = sign_extend32(ret, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case IIO_CHAN_INFO_AVERAGE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = i2c_smbus_read_word_swapped(chip->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) AD7291_T_AVERAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *val = sign_extend32(ret, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (chip->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) vref = regulator_get_voltage(chip->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (vref < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *val = vref / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *val = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *val2 = AD7291_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * One LSB of the ADC corresponds to 0.25 deg C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * The temperature reading is in 12-bit twos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * complement format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *val = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct iio_event_spec ad7291_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define AD7291_VOLTAGE_CHAN(_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .channel = _chan, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .event_spec = ad7291_events, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .num_event_specs = ARRAY_SIZE(ad7291_events), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct iio_chan_spec ad7291_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) AD7291_VOLTAGE_CHAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) AD7291_VOLTAGE_CHAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) AD7291_VOLTAGE_CHAN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) AD7291_VOLTAGE_CHAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) AD7291_VOLTAGE_CHAN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) AD7291_VOLTAGE_CHAN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) AD7291_VOLTAGE_CHAN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AD7291_VOLTAGE_CHAN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BIT(IIO_CHAN_INFO_AVERAGE_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BIT(IIO_CHAN_INFO_SCALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .channel = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .event_spec = ad7291_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .num_event_specs = ARRAY_SIZE(ad7291_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct iio_info ad7291_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .read_raw = &ad7291_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .read_event_config = &ad7291_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .write_event_config = &ad7291_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .read_event_value = &ad7291_read_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .write_event_value = &ad7291_write_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int ad7291_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct ad7291_chip_info *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mutex_init(&chip->state_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* this is only used for device removal purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) chip->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) chip->command = AD7291_NOISE_DELAY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) AD7291_T_SENSE_MASK | /* Tsense always enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) AD7291_ALERT_POLARITY; /* set irq polarity low level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) chip->reg = devm_regulator_get_optional(&client->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (IS_ERR(chip->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (PTR_ERR(chip->reg) != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return PTR_ERR(chip->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) chip->reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (chip->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = regulator_enable(chip->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) chip->command |= AD7291_EXT_REF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) indio_dev->channels = ad7291_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) indio_dev->num_channels = ARRAY_SIZE(ad7291_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) indio_dev->info = &ad7291_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = ad7291_i2c_write(chip, AD7291_COMMAND, AD7291_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = ad7291_i2c_write(chip, AD7291_COMMAND, chip->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = request_threaded_irq(client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &ad7291_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) id->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto error_unreg_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) error_unreg_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (chip->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) regulator_disable(chip->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int ad7291_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct ad7291_chip_info *chip = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) free_irq(client->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (chip->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) regulator_disable(chip->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct i2c_device_id ad7291_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { "ad7291", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DEVICE_TABLE(i2c, ad7291_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct of_device_id ad7291_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { .compatible = "adi,ad7291" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MODULE_DEVICE_TABLE(of, ad7291_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct i2c_driver ad7291_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .of_match_table = ad7291_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .probe = ad7291_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .remove = ad7291_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .id_table = ad7291_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) module_i2c_driver(ad7291_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MODULE_DESCRIPTION("Analog Devices AD7291 ADC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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