^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7266/65 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/ad7266.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct ad7266_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct spi_transfer single_xfer[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct spi_message single_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum ad7266_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum ad7266_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool fixed_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct gpio_desc *gpios[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * DMA (thus cache coherency maintenance) requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * transfer buffers to live in their own cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * The buffer needs to be large enough to hold two samples (4 bytes) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * the naturally aligned timestamp (8 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __be16 sample[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) s64 timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) } data ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int ad7266_wakeup(struct ad7266_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Any read with >= 2 bytes will wake the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return spi_read(st->spi, &st->data.sample[0], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int ad7266_powerdown(struct ad7266_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Any read with < 2 bytes will powerdown the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return spi_read(st->spi, &st->data.sample[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int ad7266_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ad7266_wakeup(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int ad7266_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return ad7266_powerdown(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .preenable = &ad7266_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .postdisable = &ad7266_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static irqreturn_t ad7266_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = spi_read(st->spi, st->data.sample, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) iio_push_to_buffers_with_timestamp(indio_dev, &st->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void ad7266_select_input(struct ad7266_state *st, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (st->fixed_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) switch (st->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case AD7266_MODE_SINGLE_ENDED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) nr >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case AD7266_MODE_PSEUDO_DIFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) nr |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case AD7266_MODE_DIFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) nr &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gpiod_set_value(st->gpios[i], (bool)(nr & BIT(i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int ad7266_update_scan_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const unsigned long *scan_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int nr = find_first_bit(scan_mask, indio_dev->masklength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ad7266_select_input(st, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int ad7266_read_single(struct ad7266_state *st, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ad7266_select_input(st, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = spi_sync(st->spi, &st->single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *val = be16_to_cpu(st->data.sample[address % 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ad7266_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct iio_chan_spec const *chan, int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long scale_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = ad7266_read_single(st, val, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *val = (*val >> 2) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (chan->scan_type.sign == 's')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *val = sign_extend32(*val, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) scale_mv = st->vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (st->mode == AD7266_MODE_DIFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) scale_mv *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (st->range == AD7266_RANGE_2VREF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) scale_mv *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *val = scale_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (st->range == AD7266_RANGE_2VREF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) st->mode != AD7266_MODE_DIFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *val = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AD7266_CHAN(_chan, _sign) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .channel = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .address = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) | BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .scan_index = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .sign = (_sign), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .shift = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AD7266_DECLARE_SINGLE_ENDED_CHANNELS(_name, _sign) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct iio_chan_spec ad7266_channels_##_name[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) AD7266_CHAN(0, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AD7266_CHAN(1, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) AD7266_CHAN(2, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) AD7266_CHAN(3, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) AD7266_CHAN(4, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) AD7266_CHAN(5, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) AD7266_CHAN(6, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) AD7266_CHAN(7, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) AD7266_CHAN(8, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) AD7266_CHAN(9, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) AD7266_CHAN(10, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) AD7266_CHAN(11, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IIO_CHAN_SOFT_TIMESTAMP(13), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AD7266_DECLARE_SINGLE_ENDED_CHANNELS_FIXED(_name, _sign) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const struct iio_chan_spec ad7266_channels_##_name##_fixed[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) AD7266_CHAN(0, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AD7266_CHAN(1, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IIO_CHAN_SOFT_TIMESTAMP(2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static AD7266_DECLARE_SINGLE_ENDED_CHANNELS(u, 'u');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static AD7266_DECLARE_SINGLE_ENDED_CHANNELS(s, 's');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static AD7266_DECLARE_SINGLE_ENDED_CHANNELS_FIXED(u, 'u');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static AD7266_DECLARE_SINGLE_ENDED_CHANNELS_FIXED(s, 's');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AD7266_CHAN_DIFF(_chan, _sign) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .type = IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .channel = (_chan) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .channel2 = (_chan) * 2 + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .address = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) | BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .scan_index = (_chan), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .sign = _sign, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .shift = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .differential = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AD7266_DECLARE_DIFF_CHANNELS(_name, _sign) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const struct iio_chan_spec ad7266_channels_diff_##_name[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) AD7266_CHAN_DIFF(0, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AD7266_CHAN_DIFF(1, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) AD7266_CHAN_DIFF(2, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) AD7266_CHAN_DIFF(3, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) AD7266_CHAN_DIFF(4, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) AD7266_CHAN_DIFF(5, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IIO_CHAN_SOFT_TIMESTAMP(6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static AD7266_DECLARE_DIFF_CHANNELS(s, 's');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static AD7266_DECLARE_DIFF_CHANNELS(u, 'u');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AD7266_DECLARE_DIFF_CHANNELS_FIXED(_name, _sign) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct iio_chan_spec ad7266_channels_diff_fixed_##_name[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AD7266_CHAN_DIFF(0, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) AD7266_CHAN_DIFF(1, (_sign)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IIO_CHAN_SOFT_TIMESTAMP(2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static AD7266_DECLARE_DIFF_CHANNELS_FIXED(s, 's');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static AD7266_DECLARE_DIFF_CHANNELS_FIXED(u, 'u');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct iio_info ad7266_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .read_raw = &ad7266_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .update_scan_mode = &ad7266_update_scan_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const unsigned long ad7266_available_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0xc00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned long ad7266_available_scan_masks_diff[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x00c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned long ad7266_available_scan_masks_fixed[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct ad7266_chan_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const unsigned long *scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define AD7266_CHAN_INFO_INDEX(_differential, _signed, _fixed) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (((_differential) << 2) | ((_signed) << 1) | ((_fixed) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct ad7266_chan_info ad7266_chan_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [AD7266_CHAN_INFO_INDEX(0, 0, 0)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .channels = ad7266_channels_u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .num_channels = ARRAY_SIZE(ad7266_channels_u),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .scan_masks = ad7266_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [AD7266_CHAN_INFO_INDEX(0, 0, 1)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .channels = ad7266_channels_u_fixed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .num_channels = ARRAY_SIZE(ad7266_channels_u_fixed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .scan_masks = ad7266_available_scan_masks_fixed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [AD7266_CHAN_INFO_INDEX(0, 1, 0)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .channels = ad7266_channels_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .num_channels = ARRAY_SIZE(ad7266_channels_s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .scan_masks = ad7266_available_scan_masks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [AD7266_CHAN_INFO_INDEX(0, 1, 1)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .channels = ad7266_channels_s_fixed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .num_channels = ARRAY_SIZE(ad7266_channels_s_fixed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .scan_masks = ad7266_available_scan_masks_fixed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) [AD7266_CHAN_INFO_INDEX(1, 0, 0)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .channels = ad7266_channels_diff_u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_channels = ARRAY_SIZE(ad7266_channels_diff_u),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .scan_masks = ad7266_available_scan_masks_diff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [AD7266_CHAN_INFO_INDEX(1, 0, 1)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .channels = ad7266_channels_diff_fixed_u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .num_channels = ARRAY_SIZE(ad7266_channels_diff_fixed_u),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .scan_masks = ad7266_available_scan_masks_fixed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [AD7266_CHAN_INFO_INDEX(1, 1, 0)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .channels = ad7266_channels_diff_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_channels = ARRAY_SIZE(ad7266_channels_diff_s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .scan_masks = ad7266_available_scan_masks_diff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [AD7266_CHAN_INFO_INDEX(1, 1, 1)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .channels = ad7266_channels_diff_fixed_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .num_channels = ARRAY_SIZE(ad7266_channels_diff_fixed_s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .scan_masks = ad7266_available_scan_masks_fixed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void ad7266_init_channels(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bool is_differential, is_signed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const struct ad7266_chan_info *chan_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) is_differential = st->mode != AD7266_MODE_SINGLE_ENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) is_signed = (st->range == AD7266_RANGE_2VREF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (st->mode == AD7266_MODE_DIFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) i = AD7266_CHAN_INFO_INDEX(is_differential, is_signed, st->fixed_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) chan_info = &ad7266_chan_infos[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) indio_dev->channels = chan_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) indio_dev->num_channels = chan_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) indio_dev->available_scan_masks = chan_info->scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) indio_dev->masklength = chan_info->num_channels - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const char * const ad7266_gpio_labels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "ad0", "ad1", "ad2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int ad7266_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct ad7266_platform_data *pdata = spi->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct ad7266_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (indio_dev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) st->reg = devm_regulator_get_optional(&spi->dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!IS_ERR(st->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = regulator_enable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = regulator_get_voltage(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) st->vref_mv = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Any other error indicates that the regulator does exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (PTR_ERR(st->reg) != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return PTR_ERR(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Use internal reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) st->vref_mv = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) st->fixed_addr = pdata->fixed_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) st->mode = pdata->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) st->range = pdata->range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!st->fixed_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < ARRAY_SIZE(st->gpios); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) st->gpios[i] = devm_gpiod_get(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ad7266_gpio_labels[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (IS_ERR(st->gpios[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = PTR_ERR(st->gpios[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) st->fixed_addr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) st->range = AD7266_RANGE_VREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) st->mode = AD7266_MODE_DIFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) st->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) indio_dev->info = &ad7266_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ad7266_init_channels(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) st->single_xfer[0].rx_buf = &st->data.sample[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) st->single_xfer[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) st->single_xfer[0].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) st->single_xfer[1].rx_buf = st->data.sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) st->single_xfer[1].len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) st->single_xfer[1].cs_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* powerdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) st->single_xfer[2].tx_buf = &st->data.sample[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) st->single_xfer[2].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spi_message_init(&st->single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) spi_message_add_tail(&st->single_xfer[0], &st->single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spi_message_add_tail(&st->single_xfer[1], &st->single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spi_message_add_tail(&st->single_xfer[2], &st->single_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &ad7266_trigger_handler, &iio_triggered_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto error_disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto error_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) error_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) error_disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int ad7266_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct ad7266_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!IS_ERR(st->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) regulator_disable(st->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct spi_device_id ad7266_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {"ad7265", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {"ad7266", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_DEVICE_TABLE(spi, ad7266_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct spi_driver ad7266_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "ad7266",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .probe = ad7266_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .remove = ad7266_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .id_table = ad7266_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) module_spi_driver(ad7266_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DESCRIPTION("Analog Devices AD7266/65 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags