^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011-2015 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/iio/adc/ad_sigma_delta.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* (AD7792)/24-bit (AD7192)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Communications Register Bit Designations (AD7192_REG_COMM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AD7192_COMM_WEN BIT(7) /* Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD7192_COMM_WRITE 0 /* Write Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD7192_COMM_READ BIT(6) /* Read Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Status Register Bit Designations (AD7192_REG_STAT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AD7192_STAT_RDY BIT(7) /* Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD7192_STAT_PARITY BIT(4) /* Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Mode Register Bit Designations (AD7192_REG_MODE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Mode Register: AD7192_MODE_SEL options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AD7192_MODE_IDLE 2 /* Idle Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Mode Register: AD7192_MODE_CLKSRC options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* from MCLK1 to MCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* available at the MCLK2 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* at the MCLK2 pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Configuration Register Bit Designations (AD7192_REG_CONF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AD7193_CH_TEMP 0x100 /* Temp senseor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* ID Register Bit Designations (AD7192_REG_ID) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CHIPID_AD7190 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CHIPID_AD7192 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CHIPID_AD7193 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CHIPID_AD7195 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AD7192_ID_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AD7192_EXT_FREQ_MHZ_MIN 2457600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AD7192_EXT_FREQ_MHZ_MAX 5120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AD7192_INT_FREQ_MHZ 4915200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AD7192_NO_SYNC_FILTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AD7192_SYNC3_FILTER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AD7192_SYNC4_FILTER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * In order to avoid contentions on the SPI bus, it's therefore necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * to use spi bus locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) AD7192_SYSCALIB_ZERO_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) AD7192_SYSCALIB_FULL_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ID_AD7190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ID_AD7192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ID_AD7193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ID_AD7195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct ad7192_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct ad7192_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct ad7192_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct regulator *avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct regulator *dvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 int_vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 f_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 scale_avail[8][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 gpocon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 clock_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct mutex lock; /* protect sensor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 syscalib_mode[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ad_sigma_delta sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const ad7192_syscalib_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) st->syscalib_mode[chan->channel] = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return st->syscalib_mode[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uintptr_t private,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool sys_calib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int ret, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = strtobool(buf, &sys_calib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) temp = st->syscalib_mode[chan->channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (sys_calib) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (temp == AD7192_SYSCALIB_ZERO_SCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct iio_enum ad7192_syscalib_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .items = ad7192_syscalib_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .set = ad7192_set_syscalib_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .get = ad7192_get_syscalib_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "sys_calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .write = ad7192_write_syscalib,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .shared = IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &ad7192_syscalib_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IIO_ENUM_AVAILABLE("sys_calibration_mode", &ad7192_syscalib_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return container_of(sd, struct ad7192_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) st->conf &= ~AD7192_CONF_CHAN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) st->conf |= AD7192_CONF_CHAN(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int ad7192_set_mode(struct ad_sigma_delta *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum ad_sigma_delta_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) st->mode &= ~AD7192_MODE_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) st->mode |= AD7192_MODE_SEL(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .set_channel = ad7192_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .set_mode = ad7192_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .has_registers = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .addr_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .read_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .irq_flags = IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int ad7192_calibrate_all(struct ad7192_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ARRAY_SIZE(ad7192_calib_arr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline bool ad7192_valid_external_frequency(u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) freq <= AD7192_EXT_FREQ_MHZ_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int ad7192_of_clock_select(struct ad7192_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct device_node *np = st->sd.spi->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int clock_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clock_sel = AD7192_CLK_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* use internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (PTR_ERR(st->mclk) == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (of_property_read_bool(np, "adi,int-clock-output-enable"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) clock_sel = AD7192_CLK_INT_CO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (of_property_read_bool(np, "adi,clock-xtal"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clock_sel = AD7192_CLK_EXT_MCLK1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clock_sel = AD7192_CLK_EXT_MCLK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return clock_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bool rej60_en, refin2_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool buf_en, bipolar, burnout_curr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long long scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int i, ret, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* reset the serial interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = ad_sd_reset(&st->sd, 48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) usleep_range(500, 1000); /* Wait for at least 500us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* write/read test for device presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) id &= AD7192_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (id != st->chip_info->chip_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) AD7192_MODE_CLKSRC(st->clock_sel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) AD7192_MODE_RATE(480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) st->conf = AD7192_CONF_GAIN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (rej60_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) st->mode |= AD7192_MODE_REJ60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) st->conf |= AD7192_CONF_REFSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) st->conf &= ~AD7192_CONF_CHOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) st->f_order = AD7192_NO_SYNC_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) buf_en = of_property_read_bool(np, "adi,buffer-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (buf_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) st->conf |= AD7192_CONF_BUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) bipolar = of_property_read_bool(np, "bipolar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!bipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) st->conf |= AD7192_CONF_UNIPOLAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) burnout_curr_en = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "adi,burnout-currents-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (burnout_curr_en && buf_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) st->conf |= AD7192_CONF_BURN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else if (burnout_curr_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_warn(&st->sd.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "Can't enable burnout currents: see CHOP or buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = ad7192_calibrate_all(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Populate available ADC input ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) scale_uv = ((u64)st->int_vref_mv * 100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) >> (indio_dev->channels[0].scan_type.realbits -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) scale_uv >>= i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) st->scale_avail[i][0] = scale_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static ssize_t ad7192_show_ac_excitation(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static ssize_t ad7192_show_bridge_switch(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static ssize_t ad7192_set(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bool val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = strtobool(buf, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) switch ((u32)this_attr->address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case AD7192_REG_GPOCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) st->gpocon |= AD7192_GPOCON_BPDSW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) st->gpocon &= ~AD7192_GPOCON_BPDSW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case AD7192_REG_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) st->mode |= AD7192_MODE_ACX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) st->mode &= ~AD7192_MODE_ACX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret ? ret : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void ad7192_get_available_filter_freq(struct ad7192_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int fadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Formulas for filter at page 25 of the datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fadc = DIV_ROUND_CLOSEST(st->fclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fadc = DIV_ROUND_CLOSEST(st->fclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static ssize_t ad7192_show_filter_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int freq_avail[4], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ad7192_get_available_filter_freq(st, freq_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) len += scnprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "%d.%d ", freq_avail[i] / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) freq_avail[i] % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0444, ad7192_show_filter_avail, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ad7192_show_bridge_switch, ad7192_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) AD7192_REG_GPOCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ad7192_show_ac_excitation, ad7192_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) AD7192_REG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct attribute *ad7192_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &iio_dev_attr_bridge_switch_en.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &iio_dev_attr_ac_excitation_en.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct attribute_group ad7192_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .attrs = ad7192_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct attribute *ad7195_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &iio_dev_attr_bridge_switch_en.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct attribute_group ad7195_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .attrs = ad7195_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static unsigned int ad7192_get_temp_scale(bool unipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return unipolar ? 2815 * 2 : 2815;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int freq_avail[4], i, ret, freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int diff_new, diff_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) diff_old = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) freq = val * 1000 + val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ad7192_get_available_filter_freq(st, freq_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) diff_new = abs(freq - freq_avail[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (diff_new < diff_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) diff_old = diff_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) switch (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) st->f_order = AD7192_SYNC4_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) st->mode &= ~AD7192_MODE_SINC3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) st->conf |= AD7192_CONF_CHOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) st->f_order = AD7192_SYNC3_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) st->mode |= AD7192_MODE_SINC3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) st->conf |= AD7192_CONF_CHOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) st->f_order = AD7192_NO_SYNC_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) st->mode &= ~AD7192_MODE_SINC3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) st->conf &= ~AD7192_CONF_CHOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) st->f_order = AD7192_NO_SYNC_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) st->mode |= AD7192_MODE_SINC3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) st->conf &= ~AD7192_CONF_CHOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int fadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fadc = DIV_ROUND_CLOSEST(st->fclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) st->f_order * AD7192_MODE_RATE(st->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (st->conf & AD7192_CONF_CHOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return DIV_ROUND_CLOSEST(fadc * 240, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (st->mode & AD7192_MODE_SINC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return DIV_ROUND_CLOSEST(fadc * 272, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return DIV_ROUND_CLOSEST(fadc * 230, 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int ad7192_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ad_sigma_delta_single_conversion(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case IIO_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!unipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *val = -(1 << (chan->scan_type.realbits - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Kelvin to Celsius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (chan->type == IIO_TEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) *val -= 273 * ad7192_get_temp_scale(unipolar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) *val = st->fclk /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *val = ad7192_get_3db_filter_freq(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *val2 = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return IIO_VAL_FRACTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int ad7192_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret, i, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (val2 == st->scale_avail[i][1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) tmp = st->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) st->conf &= ~AD7192_CONF_GAIN(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) st->conf |= AD7192_CONF_GAIN(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (tmp == st->conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 3, st->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ad7192_calibrate_all(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) div = st->fclk / (val * st->f_order * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (div < 1 || div > 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) st->mode &= ~AD7192_MODE_RATE(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) st->mode |= AD7192_MODE_RATE(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int ad7192_read_avail(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) const int **vals, int *type, int *length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) *vals = (int *)st->scale_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *type = IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Values are stored in a 2D matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *length = ARRAY_SIZE(st->scale_avail) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return IIO_AVAIL_LIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const struct iio_info ad7192_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .read_raw = ad7192_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .write_raw = ad7192_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .write_raw_get_fmt = ad7192_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .read_avail = ad7192_read_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .attrs = &ad7192_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .validate_trigger = ad_sd_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const struct iio_info ad7195_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .read_raw = ad7192_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .write_raw = ad7192_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .write_raw_get_fmt = ad7192_write_raw_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .read_avail = ad7192_read_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .attrs = &ad7195_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .validate_trigger = ad_sd_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) _type, _mask_type_av, _ext_info) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .type = (_type), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .differential = ((_channel2) == -1 ? 0 : 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .indexed = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .channel = (_channel1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .channel2 = (_channel2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .address = (_address), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .extend_name = (_extend_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .info_mask_shared_by_type_available = (_mask_type_av), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ext_info = (_ext_info), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .scan_index = (_si), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .realbits = 24, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .storagebits = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ad7192_calibsys_ext_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define AD719x_CHANNEL(_si, _channel1, _address) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define AD719x_TEMP_CHANNEL(_si, _address) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const struct iio_chan_spec ad7192_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) IIO_CHAN_SOFT_TIMESTAMP(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const struct iio_chan_spec ad7193_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) IIO_CHAN_SOFT_TIMESTAMP(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const struct ad7192_chip_info ad7192_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) [ID_AD7190] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .chip_id = CHIPID_AD7190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .name = "ad7190",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [ID_AD7192] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .chip_id = CHIPID_AD7192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .name = "ad7192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [ID_AD7193] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .chip_id = CHIPID_AD7193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .name = "ad7193",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [ID_AD7195] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .chip_id = CHIPID_AD7195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .name = "ad7195",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int ad7192_channels_config(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) switch (st->chip_info->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case CHIPID_AD7193:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) indio_dev->channels = ad7193_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) indio_dev->channels = ad7192_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int ad7192_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct ad7192_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_err(&spi->dev, "no IRQ?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) st->avdd = devm_regulator_get(&spi->dev, "avdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (IS_ERR(st->avdd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return PTR_ERR(st->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = regulator_enable(st->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (IS_ERR(st->dvdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = PTR_ERR(st->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto error_disable_avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = regulator_enable(st->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto error_disable_avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = regulator_get_voltage(st->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) goto error_disable_avdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) st->int_vref_mv = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) st->chip_info = of_device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) indio_dev->name = st->chip_info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret = ad7192_channels_config(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) goto error_disable_dvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (st->chip_info->chip_id == CHIPID_AD7195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) indio_dev->info = &ad7195_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) indio_dev->info = &ad7192_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = ad_sd_setup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto error_disable_dvdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) st->fclk = AD7192_INT_FREQ_MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) st->mclk = devm_clk_get(&st->sd.spi->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = PTR_ERR(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) goto error_remove_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) st->clock_sel = ad7192_of_clock_select(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) st->clock_sel == AD7192_CLK_EXT_MCLK2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = clk_prepare_enable(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) goto error_remove_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) st->fclk = clk_get_rate(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!ad7192_valid_external_frequency(st->fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "External clock frequency out of bounds\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) goto error_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = ad7192_setup(st, spi->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto error_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) goto error_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) error_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) st->clock_sel == AD7192_CLK_EXT_MCLK2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) clk_disable_unprepare(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) error_remove_trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) error_disable_dvdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) regulator_disable(st->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) error_disable_avdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) regulator_disable(st->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int ad7192_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct ad7192_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) st->clock_sel == AD7192_CLK_EXT_MCLK2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) clk_disable_unprepare(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) regulator_disable(st->dvdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) regulator_disable(st->avdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct of_device_id ad7192_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) MODULE_DEVICE_TABLE(of, ad7192_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static struct spi_driver ad7192_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .name = "ad7192",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .of_match_table = ad7192_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .probe = ad7192_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .remove = ad7192_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) module_spi_driver(ad7192_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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