^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD7124 SPI ADC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/adc/ad_sigma_delta.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* AD7124 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AD7124_COMMS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AD7124_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AD7124_ADC_CONTROL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AD7124_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AD7124_IO_CONTROL_1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AD7124_IO_CONTROL_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AD7124_ID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AD7124_ERROR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AD7124_ERROR_EN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AD7124_MCLK_COUNT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AD7124_CHANNEL(x) (0x09 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AD7124_CONFIG(x) (0x19 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AD7124_FILTER(x) (0x21 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AD7124_OFFSET(x) (0x29 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AD7124_GAIN(x) (0x31 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* AD7124_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* AD7124_ADC_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* AD7124 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CHIPID_AD7124_4 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CHIPID_AD7124_8 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* AD7124_CHANNEL_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AD7124_CHANNEL_EN_MSK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* AD7124_CONFIG_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* AD7124_FILTER_X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AD7124_SINC3_FILTER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AD7124_SINC4_FILTER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum ad7124_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ID_AD7124_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ID_AD7124_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum ad7124_ref_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) AD7124_REFIN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AD7124_REFIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) AD7124_INT_REF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AD7124_AVDD_REF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum ad7124_power_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AD7124_LOW_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) AD7124_MID_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AD7124_FULL_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const unsigned int ad7124_gain[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 1, 2, 4, 8, 16, 32, 64, 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const unsigned int ad7124_reg_size[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 3, 3, 3, 3, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const int ad7124_master_clk_freq_hz[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [AD7124_LOW_POWER] = 76800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [AD7124_MID_POWER] = 153600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [AD7124_FULL_POWER] = 614400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const char * const ad7124_ref_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [AD7124_REFIN1] = "refin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [AD7124_REFIN2] = "refin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [AD7124_INT_REF] = "int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [AD7124_AVDD_REF] = "avdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ad7124_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int num_inputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ad7124_channel_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum ad7124_ref_sel refsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool bipolar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool buf_positive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool buf_negative;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int ain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int pga_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int filter_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct ad7124_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct ad7124_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct ad_sigma_delta sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ad7124_channel_config *channel_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct regulator *vref[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk *mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int adc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct iio_chan_spec ad7124_channel_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .type = IIO_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .indexed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .differential = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BIT(IIO_CHAN_INFO_OFFSET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) BIT(IIO_CHAN_INFO_SAMP_FREQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .scan_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .sign = 'u',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .realbits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .storagebits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .endianness = IIO_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [ID_AD7124_4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = "ad7124-4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .chip_id = CHIPID_AD7124_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .num_inputs = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [ID_AD7124_8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "ad7124-8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .chip_id = CHIPID_AD7124_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .num_inputs = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int ad7124_find_closest_match(const int *array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int size, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int i, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int diff_new, diff_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) diff_old = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) diff_new = abs(val - array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (diff_new < diff_old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) diff_old = diff_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int ad7124_spi_write_mask(struct ad7124_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) readval &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) readval |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ad_sd_write_reg(&st->sd, addr, bytes, readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int ad7124_set_mode(struct ad_sigma_delta *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum ad_sigma_delta_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AD7124_CHANNEL_SETUP(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .set_channel = ad7124_set_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .set_mode = ad7124_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .has_registers = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .addr_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .read_mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .data_reg = AD7124_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .irq_flags = IRQF_TRIGGER_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int ad7124_set_channel_odr(struct ad7124_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int odr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int fclk, odr_sel_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) fclk = clk_get_rate(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * FS[10:0] = fCLK / (fADC x 32) where:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * fADC is the output data rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * fCLK is the master clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * FS[10:0] are the bits in the filter register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * FS[10:0] can have a value from 1 to 2047
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (odr_sel_bits < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) odr_sel_bits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else if (odr_sel_bits > 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) odr_sel_bits = 2047;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) AD7124_FILTER_FS_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) AD7124_FILTER_FS(odr_sel_bits), 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* fADC = fCLK / (FS[10:0] x 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) st->channel_config[channel].odr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int ad7124_set_channel_gain(struct ad7124_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) res = ad7124_find_closest_match(ad7124_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ARRAY_SIZE(ad7124_gain), gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) AD7124_CONFIG_PGA_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) AD7124_CONFIG_PGA(res), 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) st->channel_config[channel].pga_bits = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int fadc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) fadc = st->channel_config[channel].odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) switch (st->channel_config[channel].filter_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case AD7124_SINC3_FILTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return DIV_ROUND_CLOSEST(fadc * 230, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case AD7124_SINC4_FILTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return DIV_ROUND_CLOSEST(fadc * 262, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int ad7124_set_3db_filter_freq(struct ad7124_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int sinc4_3db_odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int sinc3_3db_odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int new_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int new_odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (sinc4_3db_odr > sinc3_3db_odr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) new_filter = AD7124_SINC3_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) new_odr = sinc4_3db_odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) new_filter = AD7124_SINC4_FILTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) new_odr = sinc3_3db_odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (st->channel_config[channel].filter_type != new_filter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) st->channel_config[channel].filter_type = new_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) AD7124_FILTER_TYPE_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) AD7124_FILTER_TYPE_SEL(new_filter),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ad7124_set_channel_odr(st, channel, new_odr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int ad7124_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int *val, int *val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct ad7124_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* After the conversion is performed, disable the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = ad_sd_write_reg(&st->sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) AD7124_CHANNEL(chan->address), 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) st->channel_config[chan->address].ain |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) AD7124_CHANNEL_EN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) idx = st->channel_config[chan->address].pga_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *val = st->channel_config[chan->address].vref_mv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (st->channel_config[chan->address].bipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *val2 = chan->scan_type.realbits - 1 + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *val2 = chan->scan_type.realbits + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (st->channel_config[chan->address].bipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *val = -(1 << (chan->scan_type.realbits - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *val = st->channel_config[chan->address].odr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int ad7124_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int val, int val2, long info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ad7124_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int res, gain, full_scale, vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (val2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ad7124_set_channel_odr(st, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (st->channel_config[chan->address].bipolar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) full_scale = 1 << (chan->scan_type.realbits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) full_scale = 1 << chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) vref = st->channel_config[chan->address].vref_mv * 1000000LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) res = DIV_ROUND_CLOSEST(vref, full_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) gain = DIV_ROUND_CLOSEST(res, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ad7124_set_channel_gain(st, chan->address, gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (val2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ad7124_set_3db_filter_freq(st, chan->address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int ad7124_reg_access(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int writeval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int *readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ad7124_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (reg >= ARRAY_SIZE(ad7124_reg_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (readval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writeval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static IIO_CONST_ATTR(in_voltage_scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct attribute *ad7124_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct attribute_group ad7124_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .attrs = ad7124_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct iio_info ad7124_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .read_raw = ad7124_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .write_raw = ad7124_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .debugfs_reg_access = &ad7124_reg_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .validate_trigger = ad_sd_validate_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .attrs = &ad7124_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int ad7124_soft_reset(struct ad7124_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int readval, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = ad_sd_reset(&st->sd, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* The AD7124 requires typically 2ms to power up and settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) usleep_range(100, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(&st->sd.spi->dev, "Soft reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int ad7124_check_chip_id(struct ad7124_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int readval, chip_id, silicon_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) chip_id = AD7124_DEVICE_ID_GET(readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) silicon_rev = AD7124_SILICON_REV_GET(readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (chip_id != st->chip_info->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(&st->sd.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "Chip ID mismatch: expected %u, got %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) st->chip_info->chip_id, chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (silicon_rev == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_err(&st->sd.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "Silicon revision empty. Chip may not be present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int ad7124_init_channel_vref(struct ad7124_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned int channel_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned int refsel = st->channel_config[channel_number].refsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) switch (refsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case AD7124_REFIN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case AD7124_REFIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case AD7124_AVDD_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (IS_ERR(st->vref[refsel])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_err(&st->sd.spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "Error, trying to use external voltage reference without a %s regulator.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ad7124_ref_names[refsel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return PTR_ERR(st->vref[refsel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) st->channel_config[channel_number].vref_mv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regulator_get_voltage(st->vref[refsel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Conversion from uV to mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) st->channel_config[channel_number].vref_mv /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case AD7124_INT_REF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) st->channel_config[channel_number].vref_mv = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 2, st->adc_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct ad7124_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct iio_chan_spec *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct ad7124_channel_config *chan_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int ain[2], channel = 0, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) st->num_channels = of_get_available_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!st->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_err(indio_dev->dev.parent, "no channel children\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sizeof(*chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) sizeof(*chan_config), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!chan_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) indio_dev->channels = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) indio_dev->num_channels = st->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) st->channel_config = chan_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = of_property_read_u32(child, "reg", &channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (channel >= indio_dev->num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(indio_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "Channel index >= number of channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = of_property_read_u32_array(child, "diff-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ain, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) AD7124_CHANNEL_AINM(ain[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) st->channel_config[channel].bipolar =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) of_property_read_bool(child, "bipolar");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = of_property_read_u32(child, "adi,reference-select", &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) st->channel_config[channel].refsel = AD7124_INT_REF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) st->channel_config[channel].refsel = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) st->channel_config[channel].buf_positive =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) of_property_read_bool(child, "adi,buffered-positive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) st->channel_config[channel].buf_negative =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) of_property_read_bool(child, "adi,buffered-negative");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) chan[channel] = ad7124_channel_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) chan[channel].address = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) chan[channel].scan_index = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) chan[channel].channel = ain[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) chan[channel].channel2 = ain[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int ad7124_setup(struct ad7124_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned int val, fclk, power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int i, ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) fclk = clk_get_rate(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!fclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* The power mode changes the master clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ARRAY_SIZE(ad7124_master_clk_freq_hz),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = clk_set_rate(st->mclk, fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Set the power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) for (i = 0; i < st->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = ad7124_init_channel_vref(st, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) tmp = (st->channel_config[i].buf_positive << 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) st->channel_config[i].buf_negative;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) AD7124_CONFIG_IN_BUFF(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * 9.38 SPS is the minimum output data rate supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * regardless of the selected power mode. Round it up to 10 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * set all the enabled channels to this default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = ad7124_set_channel_odr(st, i, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static void ad7124_reg_disable(void *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) regulator_disable(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int ad7124_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) const struct ad7124_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct ad7124_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) info = of_device_get_match_data(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) st->chip_info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) indio_dev->name = st->chip_info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) indio_dev->info = &ad7124_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (i == AD7124_INT_REF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) st->vref[i] = devm_regulator_get_optional(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ad7124_ref_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (PTR_ERR(st->vref[i]) == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) else if (IS_ERR(st->vref[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return PTR_ERR(st->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = regulator_enable(st->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) st->vref[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) st->mclk = devm_clk_get(&spi->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (IS_ERR(st->mclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return PTR_ERR(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = clk_prepare_enable(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = ad7124_soft_reset(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto error_clk_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = ad7124_check_chip_id(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) goto error_clk_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = ad7124_setup(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) goto error_clk_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = ad_sd_setup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto error_clk_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(&spi->dev, "Failed to register iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) goto error_remove_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) error_remove_trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) error_clk_disable_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) clk_disable_unprepare(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int ad7124_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct ad7124_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ad_sd_cleanup_buffer_and_trigger(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) clk_disable_unprepare(st->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const struct of_device_id ad7124_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) { .compatible = "adi,ad7124-4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) { .compatible = "adi,ad7124-8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MODULE_DEVICE_TABLE(of, ad7124_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct spi_driver ad71124_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "ad7124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .of_match_table = ad7124_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .probe = ad7124_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .remove = ad7124_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) module_spi_driver(ad71124_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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