Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AD7091RX Analog to Digital converter driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2014-2019 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "ad7091r-base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AD7091R_REG_RESULT  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AD7091R_REG_CHANNEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AD7091R_REG_CONF    2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AD7091R_REG_ALERT   3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AD7091R_REG_CH_LOW_LIMIT(ch) ((ch) * 3 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AD7091R_REG_CH_HIGH_LIMIT(ch) ((ch) * 3 + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AD7091R_REG_CH_HYSTERESIS(ch) ((ch) * 3 + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* AD7091R_REG_RESULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AD7091R_REG_RESULT_CH_ID(x)	    (((x) >> 13) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AD7091R_REG_RESULT_CONV_RESULT(x)   ((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* AD7091R_REG_CONF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD7091R_REG_CONF_AUTO   BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AD7091R_REG_CONF_CMD    BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AD7091R_REG_CONF_MODE_MASK  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	(AD7091R_REG_CONF_AUTO | AD7091R_REG_CONF_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) enum ad7091r_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	AD7091R_MODE_SAMPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	AD7091R_MODE_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	AD7091R_MODE_AUTOCYCLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct ad7091r_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct regulator *vref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	const struct ad7091r_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	enum ad7091r_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct mutex lock; /*lock to prevent concurent reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int ad7091r_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int ret, conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	case AD7091R_MODE_SAMPLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	case AD7091R_MODE_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		conf = AD7091R_REG_CONF_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case AD7091R_MODE_AUTOCYCLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		conf = AD7091R_REG_CONF_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret = regmap_update_bits(st->map, AD7091R_REG_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				 AD7091R_REG_CONF_MODE_MASK, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	st->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int ad7091r_set_channel(struct ad7091r_state *st, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	unsigned int dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* AD7091R_REG_CHANNEL specified which channels to be converted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ret = regmap_write(st->map, AD7091R_REG_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			BIT(channel) | (BIT(channel) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * There is a latency of one conversion before the channel conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * sequence is updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return regmap_read(st->map, AD7091R_REG_RESULT, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int ad7091r_read_one(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		unsigned int channel, unsigned int *read_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct ad7091r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ret = ad7091r_set_channel(st, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ret = regmap_read(st->map, AD7091R_REG_RESULT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (AD7091R_REG_RESULT_CH_ID(val) != channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	*read_val = AD7091R_REG_RESULT_CONV_RESULT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int ad7091r_read_raw(struct iio_dev *iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			   struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			   int *val, int *val2, long m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct ad7091r_state *st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned int read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (st->mode != AD7091R_MODE_COMMAND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		ret = ad7091r_read_one(iio_dev, chan->channel, &read_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		*val = read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		ret = IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (st->vref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			ret = regulator_get_voltage(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			*val = ret / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			*val = st->chip_info->vref_mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		*val2 = chan->scan_type.realbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		ret = IIO_VAL_FRACTIONAL_LOG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct iio_info ad7091r_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.read_raw = ad7091r_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static irqreturn_t ad7091r_event_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct ad7091r_state *st = (struct ad7091r_state *) private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct iio_dev *iio_dev = dev_get_drvdata(st->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned int i, read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	s64 timestamp = iio_get_time_ns(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ret = regmap_read(st->map, AD7091R_REG_ALERT, &read_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	for (i = 0; i < st->chip_info->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (read_val & BIT(i * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			iio_push_event(iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 						IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 						IIO_EV_DIR_RISING), timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (read_val & BIT(i * 2 + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			iio_push_event(iio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 					IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 						IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 						IIO_EV_DIR_FALLING), timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void ad7091r_remove(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct ad7091r_state *st = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	regulator_disable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ad7091r_probe(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		const struct ad7091r_chip_info *chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		struct regmap *map, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct iio_dev *iio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct ad7091r_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!iio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	st = iio_priv(iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	st->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	st->chip_info = chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	st->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	iio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	iio_dev->info = &ad7091r_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	iio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	iio_dev->num_channels = chip_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	iio_dev->channels = chip_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		ret = devm_request_threaded_irq(dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				ad7091r_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				IRQF_TRIGGER_FALLING | IRQF_ONESHOT, name, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	st->vref = devm_regulator_get_optional(dev, "vref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(st->vref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (PTR_ERR(st->vref) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		st->vref = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = regulator_enable(st->vref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		ret = devm_add_action_or_reset(dev, ad7091r_remove, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Use command mode by default to convert only desired channels*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	ret = ad7091r_set_mode(st, AD7091R_MODE_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return devm_iio_device_register(dev, iio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EXPORT_SYMBOL_GPL(ad7091r_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static bool ad7091r_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case AD7091R_REG_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case AD7091R_REG_ALERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static bool ad7091r_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	case AD7091R_REG_RESULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case AD7091R_REG_ALERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct regmap_config ad7091r_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.writeable_reg = ad7091r_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.volatile_reg = ad7091r_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EXPORT_SYMBOL_GPL(ad7091r_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_AUTHOR("Beniamin Bia <beniamin.bia@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DESCRIPTION("Analog Devices AD7091Rx multi-channel converters");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_LICENSE("GPL v2");