^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Sensortek STK8BA50 3-Axis Accelerometer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * STK8BA50 7-bit I2C address: 0x18.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STK8BA50_REG_XOUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STK8BA50_REG_YOUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STK8BA50_REG_ZOUT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STK8BA50_REG_RANGE 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STK8BA50_REG_BWSEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STK8BA50_REG_POWMODE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STK8BA50_REG_SWRST 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STK8BA50_REG_INTEN2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STK8BA50_REG_INTMAP2 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STK8BA50_MODE_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STK8BA50_MODE_SUSPEND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STK8BA50_MODE_POWERBIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STK8BA50_DATA_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STK8BA50_RESET_CMD 0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STK8BA50_SR_1792HZ_IDX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STK8BA50_DREADY_INT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STK8BA50_DREADY_INT_MAP 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STK8BA50_ALL_CHANNEL_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STK8BA50_ALL_CHANNEL_SIZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STK8BA50_DRIVER_NAME "stk8ba50"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STK8BA50_IRQ_NAME "stk8ba50_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STK8BA50_SCALE_AVAIL "0.0384 0.0767 0.1534 0.3069"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The accelerometer has four measurement ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * +/-2g; +/-4g; +/-8g; +/-16g
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Acceleration values are 10-bit, 2's complement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Scales are calculated as following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * scale1 = (2 + 2) * 9.81 / (2^10 - 1) = 0.0384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * scale2 = (4 + 4) * 9.81 / (2^10 - 1) = 0.0767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Scales are stored in this format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * { <register value>, <scale value> }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Locally, the range is stored as a table index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 scale_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } stk8ba50_scale_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {3, 38400}, {5, 76700}, {8, 153400}, {12, 306900}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Sample rates are stored as { <register value>, <Hz value> } */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 samp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } stk8ba50_samp_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0x08, 14}, {0x09, 25}, {0x0A, 56}, {0x0B, 112},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {0x0C, 224}, {0x0D, 448}, {0x0E, 896}, {0x0F, 1792}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Used to map scan mask bits to their corresponding channel register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const int stk8ba50_channel_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) STK8BA50_REG_XOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) STK8BA50_REG_YOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) STK8BA50_REG_ZOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct stk8ba50_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 sample_rate_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct iio_trigger *dready_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool dready_trigger_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Ensure timestamp is naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) s16 chans[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s64 timetamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STK8BA50_ACCEL_CHANNEL(index, reg, axis) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .address = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .channel2 = IIO_MOD_##axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .scan_index = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .realbits = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .shift = STK8BA50_DATA_SHIFT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .endianness = IIO_CPU, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct iio_chan_spec stk8ba50_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) STK8BA50_ACCEL_CHANNEL(0, STK8BA50_REG_XOUT, X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) STK8BA50_ACCEL_CHANNEL(1, STK8BA50_REG_YOUT, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) STK8BA50_ACCEL_CHANNEL(2, STK8BA50_REG_ZOUT, Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static IIO_CONST_ATTR(in_accel_scale_available, STK8BA50_SCALE_AVAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("14 25 56 112 224 448 896 1792");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct attribute *stk8ba50_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &iio_const_attr_in_accel_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &iio_const_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct attribute_group stk8ba50_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .attrs = stk8ba50_attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int stk8ba50_read_accel(struct stk8ba50_data *data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = i2c_smbus_read_word_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(&client->dev, "register read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int stk8ba50_data_rdy_trigger_set_state(struct iio_trigger *trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) STK8BA50_REG_INTEN2, STK8BA50_DREADY_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) STK8BA50_REG_INTEN2, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(&data->client->dev, "failed to set trigger state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) data->dready_trigger_on = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct iio_trigger_ops stk8ba50_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .set_trigger_state = stk8ba50_data_rdy_trigger_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 masked_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = i2c_smbus_read_byte_data(client, STK8BA50_REG_POWMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) goto exit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) masked_reg = ret | STK8BA50_MODE_POWERBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) masked_reg = ret & (~STK8BA50_MODE_POWERBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = i2c_smbus_write_byte_data(client, STK8BA50_REG_POWMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) masked_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) goto exit_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) exit_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(&client->dev, "failed to change sensor mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int stk8ba50_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = stk8ba50_set_power(data, STK8BA50_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = stk8ba50_read_accel(data, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *val = sign_extend32(ret >> STK8BA50_DATA_SHIFT, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *val2 = stk8ba50_scale_table[data->range].scale_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *val = stk8ba50_samp_freq_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [data->sample_rate_idx].samp_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int stk8ba50_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < ARRAY_SIZE(stk8ba50_scale_table); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (val2 == stk8ba50_scale_table[i].scale_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) STK8BA50_REG_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) stk8ba50_scale_table[index].reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "failed to set measurement range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data->range = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 0; i < ARRAY_SIZE(stk8ba50_samp_freq_table); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (val == stk8ba50_samp_freq_table[i].samp_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) STK8BA50_REG_BWSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) stk8ba50_samp_freq_table[index].reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "failed to set sampling rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) data->sample_rate_idx = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct iio_info stk8ba50_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .read_raw = stk8ba50_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .write_raw = stk8ba50_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .attrs = &stk8ba50_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static irqreturn_t stk8ba50_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int bit, ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mutex_lock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Do a bulk read if all channels are requested,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * from 0x02 (XOUT1) to 0x07 (ZOUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (*(indio_dev->active_scan_mask) == STK8BA50_ALL_CHANNEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) STK8BA50_REG_XOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) STK8BA50_ALL_CHANNEL_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) (u8 *)data->scan.chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < STK8BA50_ALL_CHANNEL_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(&data->client->dev, "register read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = stk8ba50_read_accel(data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) stk8ba50_channel_table[bit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) data->scan.chans[i++] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mutex_unlock(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static irqreturn_t stk8ba50_data_rdy_trig_poll(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (data->dready_trigger_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) iio_trigger_poll(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int stk8ba50_buffer_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return stk8ba50_set_power(data, STK8BA50_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int stk8ba50_buffer_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct iio_buffer_setup_ops stk8ba50_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .preenable = stk8ba50_buffer_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .postdisable = stk8ba50_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int stk8ba50_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct stk8ba50_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&client->dev, "iio allocation failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) indio_dev->info = &stk8ba50_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) indio_dev->name = STK8BA50_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) indio_dev->channels = stk8ba50_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) indio_dev->num_channels = ARRAY_SIZE(stk8ba50_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Reset all registers on startup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) STK8BA50_REG_SWRST, STK8BA50_RESET_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&client->dev, "failed to reset sensor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* The default range is +/-2g */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data->range = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* The default sampling rate is 1792 Hz (maximum) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) data->sample_rate_idx = STK8BA50_SR_1792HZ_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Set up interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) STK8BA50_REG_INTEN2, STK8BA50_DREADY_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(&client->dev, "failed to set up interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) STK8BA50_REG_INTMAP2, STK8BA50_DREADY_INT_MAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(&client->dev, "failed to set up interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) stk8ba50_data_rdy_trig_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) IRQF_TRIGGER_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) STK8BA50_IRQ_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(&client->dev, "request irq %d failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) data->dready_trig = devm_iio_trigger_alloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!data->dready_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) data->dready_trig->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) data->dready_trig->ops = &stk8ba50_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) iio_trigger_set_drvdata(data->dready_trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = iio_trigger_register(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&client->dev, "iio trigger register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = iio_triggered_buffer_setup(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) stk8ba50_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &stk8ba50_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(&client->dev, "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto err_trigger_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&client->dev, "device_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto err_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) err_trigger_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (data->dready_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) iio_trigger_unregister(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int stk8ba50_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct stk8ba50_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (data->dready_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) iio_trigger_unregister(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int stk8ba50_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct stk8ba50_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int stk8ba50_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct stk8ba50_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return stk8ba50_set_power(data, STK8BA50_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static SIMPLE_DEV_PM_OPS(stk8ba50_pm_ops, stk8ba50_suspend, stk8ba50_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define STK8BA50_PM_OPS (&stk8ba50_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define STK8BA50_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct i2c_device_id stk8ba50_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {"stk8ba50", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DEVICE_TABLE(i2c, stk8ba50_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct acpi_device_id stk8ba50_acpi_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {"STK8BA50", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MODULE_DEVICE_TABLE(acpi, stk8ba50_acpi_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct i2c_driver stk8ba50_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "stk8ba50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .pm = STK8BA50_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .acpi_match_table = ACPI_PTR(stk8ba50_acpi_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .probe = stk8ba50_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .remove = stk8ba50_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .id_table = stk8ba50_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) module_i2c_driver(stk8ba50_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MODULE_AUTHOR("Tiberiu Breana <tiberiu.a.breana@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MODULE_DESCRIPTION("STK8BA50 3-Axis Accelerometer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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