^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * See industrialio/accels/sca3000.h for comments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/kfifo_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCA3000_READ_REG(a) ((a) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCA3000_REG_REVID_ADDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCA3000_REG_STATUS_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCA3000_LOCKED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCA3000_EEPROM_CS_ERROR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCA3000_SPI_FRAME_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* All reads done using register decrement so no need to directly access LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCA3000_REG_X_MSB_ADDR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCA3000_REG_Y_MSB_ADDR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCA3000_REG_Z_MSB_ADDR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCA3000_REG_RING_OUT_ADDR 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Temp read untested - the e05 doesn't have the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCA3000_REG_TEMP_MSB_ADDR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCA3000_REG_MODE_ADDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCA3000_MODE_PROT_MASK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Free fall detection triggers an interrupt if the acceleration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * is below a threshold for equivalent of 25cm drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * In motion detection mode the accelerations are band pass filtered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * (approx 1 - 25Hz) and then a programmable threshold used to trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * and interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCA3000_REG_MODE_MODE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCA3000_REG_BUF_COUNT_ADDR 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCA3000_REG_INT_STATUS_ADDR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCA3000_REG_INT_STATUS_HALF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCA3000_INT_STATUS_FREE_FALL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Used to allow access to multiplexed registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCA3000_REG_CTRL_SEL_ADDR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Only available for SCA3000-D03 and SCA3000-D01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * will not function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Control which motion detector interrupts are on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * For now only OR combinations are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCA3000_MD_CTRL_PROT_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SCA3000_MD_CTRL_OR_Y BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCA3000_MD_CTRL_OR_X BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCA3000_MD_CTRL_OR_Z BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Currently unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCA3000_MD_CTRL_AND_Y BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCA3000_MD_CTRL_AND_X BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCA3000_MD_CTRL_AND_Z BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Some control registers of complex access methods requiring this register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * be used to remove a lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SCA3000_REG_UNLOCK_ADDR 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SCA3000_REG_INT_MASK_ADDR 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SCA3000_REG_INT_MASK_ALL_INTS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Values of multiplexed registers (write to ctrl_data after select) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SCA3000_REG_CTRL_DATA_ADDR 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Measurement modes available on some sca3000 series chips. Code assumes others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * may become available in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Bypass - Bypass the low-pass filter in the signal channel so as to increase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * signal bandwidth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Narrow - Narrow low-pass filtering of the signal channel and half output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * data rate by decimation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Wide - Widen low-pass filtering of signal channel to increase bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SCA3000_OP_MODE_BYPASS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SCA3000_OP_MODE_NARROW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SCA3000_OP_MODE_WIDE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SCA3000_MAX_TX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SCA3000_MAX_RX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * struct sca3000_state - device instance state information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @us: the associated spi device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @info: chip variant information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @last_timestamp: the timestamp of the last event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @mo_det_use_count: reference counter for the motion detection unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @lock: lock used to protect elements of sca3000_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * and the underlying device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @tx: dma-able transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @rx: dma-able receive buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct sca3000_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct spi_device *us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct sca3000_chip_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) s64 last_timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int mo_det_use_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Can these share a cacheline ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 rx[384] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 tx[6] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * struct sca3000_chip_info - model dependent parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @scale: scale * 10^-6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @temp_output: some devices have temperature sensors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @measurement_mode_freq: normal mode sampling frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * the normal measurement mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @option_mode_1: first optional mode. Not all models have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @option_mode_1_freq: option mode 1 sampling frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * the first option mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @option_mode_2: second optional mode. Not all chips have one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @option_mode_2_freq: option mode 2 sampling frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * the second option mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @mot_det_mult_xz: Bit wise multipliers to calculate the threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * for motion detection in the x and z axis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @mot_det_mult_y: Bit wise multipliers to calculate the threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * for motion detection in the y axis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * This structure is used to hold information about the functionality of a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * sca3000 variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct sca3000_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool temp_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int measurement_mode_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int measurement_mode_3db_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int option_mode_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int option_mode_1_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int option_mode_1_3db_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int option_mode_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int option_mode_2_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int option_mode_2_3db_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int mot_det_mult_xz[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int mot_det_mult_y[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enum sca3000_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) d01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) e02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) e04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) e05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Note where option modes are not defined, the chip simply does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * support any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Other chips in the sca3000 series use i2c and are not included here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Some of these devices are only listed in the family data sheet and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * do not actually appear to be available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [d01] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .scale = 7357,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .temp_output = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .measurement_mode_freq = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .measurement_mode_3db_freq = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .option_mode_1 = SCA3000_OP_MODE_BYPASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .option_mode_1_freq = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .option_mode_1_3db_freq = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [e02] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .scale = 9810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .measurement_mode_freq = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .measurement_mode_3db_freq = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .option_mode_1 = SCA3000_OP_MODE_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .option_mode_1_freq = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .option_mode_1_3db_freq = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [e04] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .scale = 19620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .measurement_mode_freq = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .measurement_mode_3db_freq = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .option_mode_1 = SCA3000_OP_MODE_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .option_mode_1_freq = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .option_mode_1_3db_freq = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .option_mode_2 = SCA3000_OP_MODE_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .option_mode_2_freq = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .option_mode_2_3db_freq = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [e05] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .scale = 61313,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .measurement_mode_freq = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .measurement_mode_3db_freq = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .option_mode_1 = SCA3000_OP_MODE_NARROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .option_mode_1_freq = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .option_mode_1_3db_freq = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .option_mode_2 = SCA3000_OP_MODE_WIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .option_mode_2_freq = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .option_mode_2_3db_freq = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) st->tx[0] = SCA3000_WRITE_REG(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) st->tx[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return spi_write(st->us, st->tx, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int sca3000_read_data_short(struct sca3000_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 reg_address_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct spi_transfer xfer[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .tx_buf = st->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .rx_buf = st->rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) st->tx[0] = SCA3000_READ_REG(reg_address_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * sca3000_reg_lock_on() - test if the ctrl register lock is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @st: Driver specific device instance data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Lock must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int sca3000_reg_lock_on(struct sca3000_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return !(st->rx[0] & SCA3000_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * __sca3000_unlock_reg_lock() - unlock the control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * @st: Driver specific device instance data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Note the device does not appear to support doing this in a single transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * This should only ever be used as part of ctrl reg read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Lock must be held before calling this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct spi_transfer xfer[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .tx_buf = st->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .tx_buf = st->tx + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .tx_buf = st->tx + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) st->tx[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) st->tx[3] = 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) st->tx[5] = 0xA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * sca3000_write_ctrl_reg() write to a lock protect ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @st: Driver specific device instance data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @sel: selects which registers we wish to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @val: the value to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Certain control registers are protected against overwriting by the lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * register and use a shared write address. This function allows writing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * these registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Lock must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int sca3000_write_ctrl_reg(struct sca3000_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) uint8_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = sca3000_reg_lock_on(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = __sca3000_unlock_reg_lock(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Set the control select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Write the actual value into the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * sca3000_read_ctrl_reg() read from lock protected control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @st: Driver specific device instance data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * @ctrl_reg: Which ctrl register do we want to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * Lock must be held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int sca3000_read_ctrl_reg(struct sca3000_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 ctrl_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = sca3000_reg_lock_on(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = __sca3000_unlock_reg_lock(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Set the control select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return st->rx[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * sca3000_show_rev() - sysfs interface to read the chip revision number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * @indio_dev: Device instance specific generic IIO data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Driver specific device instance data can be obtained via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * via iio_priv(indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int sca3000_print_rev(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_info(&indio_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "sca3000 revision major=%lu, minor=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) sca3000_show_available_3db_freqs(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (st->info->option_mode_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) len += sprintf(buf + len, " %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) st->info->option_mode_1_3db_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (st->info->option_mode_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) len += sprintf(buf + len, " %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) st->info->option_mode_2_3db_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) len += sprintf(buf + len, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) S_IRUGO, sca3000_show_available_3db_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct iio_event_spec sca3000_event = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .type = IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .dir = IIO_EV_DIR_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Note the hack in the number of bits to pretend we have 2 more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * we do in the fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SCA3000_CHAN(index, mod) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .channel2 = mod, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .address = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .scan_index = index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .realbits = 13, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .shift = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .endianness = IIO_BE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .event_spec = &sca3000_event, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .num_event_specs = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct iio_event_spec sca3000_freefall_event_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .type = IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .dir = IIO_EV_DIR_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BIT(IIO_EV_INFO_PERIOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct iio_chan_spec sca3000_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SCA3000_CHAN(0, IIO_MOD_X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SCA3000_CHAN(1, IIO_MOD_Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SCA3000_CHAN(2, IIO_MOD_Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .type = IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .channel2 = IIO_MOD_X_AND_Y_AND_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .scan_index = -1, /* Fake channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .event_spec = &sca3000_freefall_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .num_event_specs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct iio_chan_spec sca3000_channels_with_temp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) SCA3000_CHAN(0, IIO_MOD_X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) SCA3000_CHAN(1, IIO_MOD_Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SCA3000_CHAN(2, IIO_MOD_Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .type = IIO_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) BIT(IIO_CHAN_INFO_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* No buffer support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .scan_index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .type = IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .modified = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .channel2 = IIO_MOD_X_AND_Y_AND_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .scan_index = -1, /* Fake channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .event_spec = &sca3000_freefall_event_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .num_event_specs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static u8 sca3000_addresses[3][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SCA3000_MD_CTRL_OR_X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SCA3000_MD_CTRL_OR_Y},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SCA3000_MD_CTRL_OR_Z},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * __sca3000_get_base_freq() - obtain mode specific base frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @st: Private driver specific device instance specific state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @info: chip type specific information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @base_freq: Base frequency for the current measurement mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static inline int __sca3000_get_base_freq(struct sca3000_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) const struct sca3000_chip_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int *base_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) *base_freq = info->measurement_mode_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case SCA3000_REG_MODE_MEAS_MODE_OP_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) *base_freq = info->option_mode_1_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case SCA3000_REG_MODE_MEAS_MODE_OP_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) *base_freq = info->option_mode_2_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @st: Private driver specific device instance specific state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @val: The frequency read back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = __sca3000_get_base_freq(st, st->info, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (*val > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *val /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *val /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * @st: Private driver specific device instance specific state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @val: The frequency desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int ret, base_freq, ctrlval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = __sca3000_get_base_freq(st, st->info, &base_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (val == base_freq / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (val == base_freq / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else if (val != base_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ctrlval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* mask bottom 2 bits - only ones that are relevant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) switch (st->rx[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *val = st->info->measurement_mode_3db_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case SCA3000_REG_MODE_MEAS_MODE_OP_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) *val = st->info->option_mode_1_3db_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case SCA3000_REG_MODE_MEAS_MODE_OP_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) *val = st->info->option_mode_2_3db_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (val == st->info->measurement_mode_3db_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else if (st->info->option_mode_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (val == st->info->option_mode_1_3db_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) else if (st->info->option_mode_2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) (val == st->info->option_mode_2_3db_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int sca3000_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (chan->type == IIO_ACCEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (st->mo_det_use_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) address = sca3000_addresses[chan->address][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = sca3000_read_data_short(st, address, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) *val = (be16_to_cpup((__be16 *)st->rx) >> 3) & 0x1FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *val = ((*val) << (sizeof(*val) * 8 - 13)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) (sizeof(*val) * 8 - 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* get the temperature when available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = sca3000_read_data_short(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SCA3000_REG_TEMP_MSB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *val = ((st->rx[0] & 0x3F) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ((st->rx[1] & 0xE0) >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (chan->type == IIO_ACCEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) *val2 = st->info->scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) else /* temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *val2 = 555556;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *val = -214;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *val2 = 600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = sca3000_read_raw_samp_freq(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return ret ? ret : IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = sca3000_read_3db_freq(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int sca3000_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = sca3000_write_raw_samp_freq(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = sca3000_write_3db_freq(st, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * sca3000_read_av_freq() - sysfs function to get available frequencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * @dev: Device structure for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * @attr: Description of the attribute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * @buf: Incoming string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * The later modes are only relevant to the ring buffer - and depend on current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * mode. Note that data sheet gives rather wide tolerances for these so integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * division will give good enough answer and not all chips have them specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static ssize_t sca3000_read_av_freq(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int len = 0, ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) val = st->rx[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) switch (val & SCA3000_REG_MODE_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) len += sprintf(buf + len, "%d %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) st->info->measurement_mode_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) st->info->measurement_mode_freq / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) st->info->measurement_mode_freq / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case SCA3000_REG_MODE_MEAS_MODE_OP_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) len += sprintf(buf + len, "%d %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) st->info->option_mode_1_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) st->info->option_mode_1_freq / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) st->info->option_mode_1_freq / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case SCA3000_REG_MODE_MEAS_MODE_OP_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) len += sprintf(buf + len, "%d %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) st->info->option_mode_2_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) st->info->option_mode_2_freq / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) st->info->option_mode_2_freq / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * Should only really be registered if ring buffer support is compiled in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * Does no harm however and doing it right would add a fair bit of complexity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * sca3000_read_event_value() - query of a threshold or period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int sca3000_read_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = sca3000_read_ctrl_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) sca3000_addresses[chan->address][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (chan->channel2 == IIO_MOD_Y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) for_each_set_bit(i, &ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ARRAY_SIZE(st->info->mot_det_mult_y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) *val += st->info->mot_det_mult_y[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) for_each_set_bit(i, &ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ARRAY_SIZE(st->info->mot_det_mult_xz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) *val += st->info->mot_det_mult_xz[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *val2 = 226000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * sca3000_write_value() - control of threshold and period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * @indio_dev: Device instance specific IIO information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * @chan: Description of the channel for which the event is being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * @type: The type of event being configured, here magnitude rising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * as everything else is read only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * @dir: Direction of the event (here rising)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * @info: What information about the event are we configuring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Here the threshold only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * @val: Integer part of the value being written..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * @val2: Non integer part of the value being written. Here always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int sca3000_write_event_value(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u8 nonlinear = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (chan->channel2 == IIO_MOD_Y) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) i = ARRAY_SIZE(st->info->mot_det_mult_y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) while (i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (val >= st->info->mot_det_mult_y[--i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) nonlinear |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) val -= st->info->mot_det_mult_y[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) i = ARRAY_SIZE(st->info->mot_det_mult_xz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) while (i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (val >= st->info->mot_det_mult_xz[--i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) nonlinear |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) val -= st->info->mot_det_mult_xz[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = sca3000_write_ctrl_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sca3000_addresses[chan->address][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) nonlinear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static struct attribute *sca3000_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const struct attribute_group sca3000_attribute_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .attrs = sca3000_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int sca3000_read_data(struct sca3000_state *st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u8 reg_address_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u8 *rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct spi_transfer xfer[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .tx_buf = st->tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .rx_buf = rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) st->tx[0] = SCA3000_READ_REG(reg_address_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev_err(&st->us->dev, "problem reading register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * sca3000_ring_int_process() - ring specific interrupt handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * @val: Value of the interrupt status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * @indio_dev: Device instance specific IIO device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int ret, i, num_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (val & SCA3000_REG_INT_STATUS_HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) num_available = st->rx[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * num_available is the total number of samples available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * i.e. number of time points * number of channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) num_available * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) for (i = 0; i < num_available / 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * Dirty hack to cover for 11 bit in fifo, 13 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * direct reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * In theory the bottom two bits are undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * In reality they appear to always be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * sca3000_event_handler() - handling ring and non ring events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * @irq: The irq being handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * @private: struct iio_device pointer for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Ring related interrupt handler. Depending on event, push to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * the ring buffer event chrdev or the event one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * This function is complicated by the fact that the devices can signify ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * and non ring events via the same interrupt line and they can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * be distinguished via a read of the relevant status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static irqreturn_t sca3000_event_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) s64 last_timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * Could lead if badly timed to an extra read of status reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * but ensures no interrupt is missed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) val = st->rx[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) sca3000_ring_int_process(val, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (val & SCA3000_INT_STATUS_FREE_FALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) IIO_MOD_X_AND_Y_AND_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) last_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (val & SCA3000_INT_STATUS_Y_TRIGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) IIO_MOD_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) last_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (val & SCA3000_INT_STATUS_X_TRIGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) IIO_MOD_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) last_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (val & SCA3000_INT_STATUS_Z_TRIGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) IIO_MOD_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) IIO_EV_TYPE_MAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) last_timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * sca3000_read_event_config() what events are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static int sca3000_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* read current value of mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) switch (chan->channel2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case IIO_MOD_X_AND_Y_AND_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case IIO_MOD_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case IIO_MOD_Y:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) case IIO_MOD_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * Motion detection mode cannot run at the same time as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * acceleration data being read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret = sca3000_read_ctrl_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SCA3000_REG_CTRL_SEL_MD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* only supporting logical or's for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ret = !!(ret & sca3000_addresses[chan->address][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* read current value of mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* if off and should be on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* if on and should be off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int ret, ctrlval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * First read the motion detector config to find out if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * this axis is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ctrlval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* if off and should be on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (state && !(ctrlval & sca3000_addresses[axis][2])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = sca3000_write_ctrl_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SCA3000_REG_CTRL_SEL_MD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ctrlval |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) sca3000_addresses[axis][2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) st->mo_det_use_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret = sca3000_write_ctrl_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SCA3000_REG_CTRL_SEL_MD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ctrlval &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ~(sca3000_addresses[axis][2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) st->mo_det_use_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* read current value of mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* if off and should be on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if ((st->mo_det_use_count) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) | SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* if on and should be off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) else if (!(st->mo_det_use_count) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * sca3000_write_event_config() - simple on off control for motion detector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * @indio_dev: IIO device instance specific structure. Data specific to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * particular driver may be accessed via iio_priv(indio_dev).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * @chan: Description of the channel whose event we are configuring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * @type: The type of event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * @dir: The direction of the event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * @state: Desired state of event being configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * This is a per axis control, but enabling any will result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * motion detector unit being enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * N.B. enabling motion detector stops normal data acquisition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * There is a complexity in knowing which mode to return to when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * this mode is disabled. Currently normal mode is assumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static int sca3000_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) switch (chan->channel2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) case IIO_MOD_X_AND_Y_AND_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ret = sca3000_freefall_set_state(indio_dev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) case IIO_MOD_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case IIO_MOD_Y:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case IIO_MOD_Z:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = sca3000_motion_detect_set_state(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) chan->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int sca3000_configure_ring(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct iio_buffer *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) buffer = devm_iio_kfifo_allocate(&indio_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) iio_device_attach_buffer(indio_dev, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ret = sca3000_write_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ret = sca3000_write_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * sca3000_hw_ring_preenable() - hw ring buffer preenable function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * @indio_dev: structure representing the IIO device. Device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * specific state can be accessed via iio_priv(indio_dev).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Very simple enable function as the chip will allows normal reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * during ring buffer operation so as long as it is indeed running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * before we notify the core, the precise ordering does not matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Enable the 50% full interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto error_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ret = sca3000_write_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) SCA3000_REG_INT_MASK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) goto error_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return __sca3000_hw_ring_state_set(indio_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) error_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = __sca3000_hw_ring_state_set(indio_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* Disable the 50% full interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = sca3000_write_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) SCA3000_REG_INT_MASK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .preenable = &sca3000_hw_ring_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .postdisable = &sca3000_hw_ring_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * sca3000_clean_setup() - get the device into a predictable state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * @st: Device instance specific private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * Devices use flash memory to store many of the register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * and hence can come up in somewhat unpredictable states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * Hence reset everything on driver load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static int sca3000_clean_setup(struct sca3000_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Ensure all interrupts have been acknowledged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* Turn off all motion detection channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ret & SCA3000_MD_CTRL_PROT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* Disable ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) | SCA3000_REG_OUT_CTRL_BUF_X_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) | SCA3000_REG_OUT_CTRL_BUF_Y_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) | SCA3000_REG_OUT_CTRL_BUF_Z_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Enable interrupts, relevant to mode and set up as active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = sca3000_write_reg(st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SCA3000_REG_INT_MASK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) (ret & SCA3000_REG_INT_MASK_PROT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) | SCA3000_REG_INT_MASK_ACTIVE_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * Select normal measurement mode, free fall off, ring off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * as that occurs in one of the example on the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) (st->rx[0] & SCA3000_MODE_PROT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static const struct iio_info sca3000_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .attrs = &sca3000_attribute_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .read_raw = &sca3000_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .write_raw = &sca3000_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .read_event_value = &sca3000_read_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .write_event_value = &sca3000_write_event_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .read_event_config = &sca3000_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .write_event_config = &sca3000_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static int sca3000_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct sca3000_state *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) spi_set_drvdata(spi, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) st->us = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) mutex_init(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) indio_dev->name = spi_get_device_id(spi)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) indio_dev->info = &sca3000_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (st->info->temp_output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) indio_dev->channels = sca3000_channels_with_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) indio_dev->num_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ARRAY_SIZE(sca3000_channels_with_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) indio_dev->channels = sca3000_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ret = sca3000_configure_ring(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ret = request_threaded_irq(spi->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) &sca3000_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) "sca3000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) indio_dev->setup_ops = &sca3000_ring_setup_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ret = sca3000_clean_setup(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) goto error_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ret = sca3000_print_rev(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) goto error_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) error_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (spi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) free_irq(spi->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int sca3000_stop_all_interrupts(struct sca3000_state *st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) mutex_lock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) goto error_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) (st->rx[0] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SCA3000_REG_INT_MASK_RING_HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SCA3000_REG_INT_MASK_ALL_INTS)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) error_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) mutex_unlock(&st->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static int sca3000_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct iio_dev *indio_dev = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct sca3000_state *st = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Must ensure no interrupts can be generated after this! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) sca3000_stop_all_interrupts(st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (spi->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) free_irq(spi->irq, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static const struct spi_device_id sca3000_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {"sca3000_d01", d01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {"sca3000_e02", e02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {"sca3000_e04", e04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {"sca3000_e05", e05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) MODULE_DEVICE_TABLE(spi, sca3000_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static struct spi_driver sca3000_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .name = "sca3000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .probe = sca3000_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .remove = sca3000_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .id_table = sca3000_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) module_spi_driver(sca3000_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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