Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * 3-axis accelerometer driver for MXC4005XC Memsic sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MXC4005_DRV_NAME		"mxc4005"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MXC4005_IRQ_NAME		"mxc4005_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MXC4005_REGMAP_NAME		"mxc4005_regmap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MXC4005_REG_XOUT_UPPER		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MXC4005_REG_XOUT_LOWER		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MXC4005_REG_YOUT_UPPER		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MXC4005_REG_YOUT_LOWER		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MXC4005_REG_ZOUT_UPPER		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MXC4005_REG_ZOUT_LOWER		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MXC4005_REG_INT_MASK1		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MXC4005_REG_INT_MASK1_BIT_DRDYE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MXC4005_REG_INT_CLR1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MXC4005_REG_INT_CLR1_BIT_DRDYC	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MXC4005_REG_CONTROL		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MXC4005_REG_CONTROL_MASK_FSR	GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MXC4005_CONTROL_FSR_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MXC4005_REG_DEVICE_ID		0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) enum mxc4005_axis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	AXIS_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	AXIS_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	AXIS_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) enum mxc4005_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	MXC4005_RANGE_2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	MXC4005_RANGE_4G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	MXC4005_RANGE_8G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) struct mxc4005_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct iio_trigger *dready_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* Ensure timestamp is naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		__be16 chans[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		s64 timestamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	} scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	bool trigger_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * MXC4005 can operate in the following ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * +/- 2G, 4G, 8G (the default +/-2G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) } mxc4005_scale_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{MXC4005_RANGE_2G, 9582},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{MXC4005_RANGE_4G, 19164},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{MXC4005_RANGE_8G, 38329},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static struct attribute *mxc4005_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	&iio_const_attr_in_accel_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const struct attribute_group mxc4005_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.attrs = mxc4005_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case MXC4005_REG_XOUT_UPPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case MXC4005_REG_XOUT_LOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case MXC4005_REG_YOUT_UPPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case MXC4005_REG_YOUT_LOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case MXC4005_REG_ZOUT_UPPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	case MXC4005_REG_ZOUT_LOWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case MXC4005_REG_DEVICE_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case MXC4005_REG_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case MXC4005_REG_INT_CLR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case MXC4005_REG_INT_MASK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case MXC4005_REG_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct regmap_config mxc4005_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.name = MXC4005_REGMAP_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.max_register = MXC4005_REG_DEVICE_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.readable_reg = mxc4005_is_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.writeable_reg = mxc4005_is_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int mxc4005_read_xyz(struct mxc4005_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			       data->scan.chans, sizeof(data->scan.chans));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		dev_err(data->dev, "failed to read axes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int mxc4005_read_axis(struct mxc4005_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			     unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	__be16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret = regmap_bulk_read(data->regmap, addr, &reg, sizeof(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		dev_err(data->dev, "failed to read reg %02x\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return be16_to_cpu(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int mxc4005_read_scale(struct mxc4005_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		dev_err(data->dev, "failed to read reg_control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	i = reg >> MXC4005_CONTROL_FSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return mxc4005_scale_table[i].scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int mxc4005_set_scale(struct mxc4005_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (mxc4005_scale_table[i].scale == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			reg = i << MXC4005_CONTROL_FSR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			ret = regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 						 MXC4005_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 						 MXC4005_REG_CONTROL_MASK_FSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 						 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				dev_err(data->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					"failed to write reg_control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int mxc4005_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			    struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			    int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct mxc4005_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			ret = mxc4005_read_axis(data, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			*val = sign_extend32(ret >> chan->scan_type.shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					     chan->scan_type.realbits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		ret = mxc4005_read_scale(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		*val2 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int mxc4005_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			     struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			     int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct mxc4005_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (val != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return mxc4005_set_scale(data, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct iio_info mxc4005_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.read_raw	= mxc4005_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.write_raw	= mxc4005_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.attrs		= &mxc4005_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const unsigned long mxc4005_scan_masks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MXC4005_CHANNEL(_axis, _addr) {				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.type = IIO_ACCEL,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.modified = 1,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.channel2 = IIO_MOD_##_axis,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.address = _addr,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.scan_index = AXIS_##_axis,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.scan_type = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.sign = 's',					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.realbits = 12,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.storagebits = 16,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.shift = 4,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.endianness = IIO_BE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct iio_chan_spec mxc4005_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static irqreturn_t mxc4005_trigger_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct iio_poll_func *pf = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct mxc4005_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	ret = mxc4005_read_xyz(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					   pf->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int mxc4005_clr_intr(struct mxc4005_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	/* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			   MXC4005_REG_INT_CLR1_BIT_DRDYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dev_err(data->dev, "failed to write to reg_int_clr1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int mxc4005_set_trigger_state(struct iio_trigger *trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				     bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct mxc4005_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				   MXC4005_REG_INT_MASK1_BIT_DRDYE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				   ~MXC4005_REG_INT_MASK1_BIT_DRDYE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		dev_err(data->dev, "failed to update reg_int_mask1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	data->trigger_enabled = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct mxc4005_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (!data->dready_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return mxc4005_clr_intr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct iio_trigger_ops mxc4005_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.set_trigger_state = mxc4005_set_trigger_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.try_reenable = mxc4005_trigger_try_reen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int mxc4005_chip_init(struct mxc4005_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		dev_err(data->dev, "failed to read chip id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int mxc4005_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct mxc4005_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		dev_err(&client->dev, "failed to initialize regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	data->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	ret = mxc4005_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		dev_err(&client->dev, "failed to initialize chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	indio_dev->channels = mxc4005_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	indio_dev->available_scan_masks = mxc4005_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	indio_dev->name = MXC4005_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	indio_dev->info = &mxc4005_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 					 iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 					 mxc4005_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 					 NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			"failed to setup iio triggered buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		data->dready_trig = devm_iio_trigger_alloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 							   "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 							   indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 							   indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		if (!data->dready_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 						iio_trigger_generic_data_rdy_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 						NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 						IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 						IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 						MXC4005_IRQ_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 						data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 				"failed to init threaded irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		data->dready_trig->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		data->dready_trig->ops = &mxc4005_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		iio_trigger_set_drvdata(data->dready_trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		indio_dev->trig = data->dready_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		iio_trigger_get(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		ret = devm_iio_trigger_register(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 						data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 				"failed to register trigger\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct acpi_device_id mxc4005_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	{"MXC4005",	0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	{"MXC6655",	0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct i2c_device_id mxc4005_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	{"mxc4005",	0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	{"mxc6655",	0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_DEVICE_TABLE(i2c, mxc4005_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct i2c_driver mxc4005_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		.name = MXC4005_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		.acpi_match_table = ACPI_PTR(mxc4005_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	.probe		= mxc4005_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	.id_table	= mxc4005_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) module_i2c_driver(mxc4005_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver");