^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * KXCJK-1013 3-axis accelerometer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iio/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iio/accel/kxcjk_1013.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define KXCJK1013_DRV_NAME "kxcjk1013"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define KXCJK1013_IRQ_NAME "kxcjk1013_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define KXTF9_REG_HP_XOUT_L 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define KXTF9_REG_HP_XOUT_H 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define KXTF9_REG_HP_YOUT_L 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define KXTF9_REG_HP_YOUT_H 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define KXTF9_REG_HP_ZOUT_L 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define KXTF9_REG_HP_ZOUT_H 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define KXCJK1013_REG_XOUT_L 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * From low byte X axis register, all the other addresses of Y and Z can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * obtained by just applying axis offset. The following axis defines are just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * provide clarity, but not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define KXCJK1013_REG_XOUT_H 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define KXCJK1013_REG_YOUT_L 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define KXCJK1013_REG_YOUT_H 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define KXCJK1013_REG_ZOUT_L 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define KXCJK1013_REG_ZOUT_H 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define KXCJK1013_REG_DCST_RESP 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define KXCJK1013_REG_WHO_AM_I 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define KXTF9_REG_TILT_POS_CUR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define KXTF9_REG_TILT_POS_PREV 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define KXTF9_REG_INT_SRC1 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define KXCJK1013_REG_INT_SRC1 0x16 /* compatible, but called INT_SRC2 in KXTF9 ds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define KXCJK1013_REG_INT_SRC2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define KXCJK1013_REG_STATUS_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define KXCJK1013_REG_INT_REL 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define KXCJK1013_REG_CTRL1 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define KXTF9_REG_CTRL2 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define KXCJK1013_REG_CTRL2 0x1D /* mostly compatible, CTRL_REG3 in KTXF9 ds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define KXCJK1013_REG_INT_CTRL1 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define KXCJK1013_REG_INT_CTRL2 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define KXTF9_REG_INT_CTRL3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define KXCJK1013_REG_DATA_CTRL 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define KXTF9_REG_TILT_TIMER 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define KXCJK1013_REG_WAKE_TIMER 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define KXTF9_REG_TDT_TIMER 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define KXTF9_REG_TDT_THRESH_H 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KXTF9_REG_TDT_THRESH_L 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KXTF9_REG_TDT_TAP_TIMER 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define KXTF9_REG_TDT_LATENCY_TIMER 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define KXTF9_REG_TDT_WINDOW_TIMER 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define KXCJK1013_REG_SELF_TEST 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define KXTF9_REG_WAKE_THRESH 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define KXTF9_REG_TILT_ANGLE 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define KXTF9_REG_HYST_SET 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define KXCJK1013_REG_WAKE_THRES 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define KXCJK1013_MAX_STARTUP_TIME_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define KXCJK1013_SLEEP_DELAY_MS 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define KXCJK1013_DEFAULT_WAKE_THRES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum kx_chipset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) KXCJK1013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) KXCJ91008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) KXTJ21009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) KXTF9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) KX_MAX_CHIPS /* this must be last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum kx_acpi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ACPI_GENERIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ACPI_SMO8500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ACPI_KIOX010A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum kxcjk1013_axis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) AXIS_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) AXIS_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) AXIS_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) AXIS_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct kxcjk1013_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct iio_trigger *dready_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct iio_trigger *motion_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct iio_mount_matrix orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Ensure timestamp naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) s16 chans[AXIS_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) s64 timestamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 odr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int wake_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int wake_dur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool active_high_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool dready_trigger_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ev_enable_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool motion_trigger_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int64_t timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum kx_chipset chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum kx_acpi_type acpi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum kxcjk1013_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) STANDBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) OPERATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) enum kxcjk1013_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) KXCJK1013_RANGE_2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) KXCJK1013_RANGE_4G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) KXCJK1013_RANGE_8G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct kx_odr_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int odr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int wuf_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct kx_odr_map samp_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0, 781000, 0x08, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 1, 563000, 0x09, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 3, 125000, 0x0A, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 6, 250000, 0x0B, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 12, 500000, 0x00, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 25, 0, 0x01, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 50, 0, 0x02, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 100, 0, 0x03, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 200, 0, 0x04, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 400, 0, 0x05, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 800, 0, 0x06, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 1600, 0, 0x07, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char *const kxcjk1013_samp_freq_avail =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct kx_odr_map kxtf9_samp_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 25, 0, 0x01, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 50, 0, 0x02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 100, 0, 0x03, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 200, 0, 0x04, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 400, 0, 0x05, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 800, 0, 0x06, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char *const kxtf9_samp_freq_avail =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "25 50 100 200 400 800";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Refer to section 4 of the specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int odr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } odr_start_up_times[KX_MAX_CHIPS][12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* KXCJK-1013 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x08, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x09, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x0A, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x0B, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x01, 41000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x02, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x03, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x04, 6400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x05, 3900},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x06, 2700},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x07, 2100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* KXCJ9-1008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x08, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x09, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x0A, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x0B, 100000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x01, 41000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x02, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x03, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x04, 6400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x05, 3900},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x06, 2700},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x07, 2100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* KXCTJ2-1009 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x08, 1240000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x09, 621000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x0A, 309000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x0B, 151000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0, 80000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x01, 41000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x02, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x03, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x04, 6000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x05, 4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x06, 3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x07, 2000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* KXTF9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x01, 81000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x02, 41000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x03, 21000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x04, 11000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x05, 5100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x06, 2700},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u16 scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 gsel_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 gsel_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } KXCJK1013_scale_table[] = { {9582, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {19163, 1, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {38326, 0, 1} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum kiox010a_fn_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) KIOX010A_SET_LAPTOP_MODE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) KIOX010A_SET_TABLET_MODE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int kiox010a_dsm(struct device *dev, int fn_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) acpi_handle handle = ACPI_HANDLE(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) guid_t kiox010a_dsm_guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) guid_parse("1f339696-d475-4e26-8cad-2e9f8e6d7a91", &kiox010a_dsm_guid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) obj = acpi_evaluate_dsm(handle, &kiox010a_dsm_guid, 1, fn_index, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ACPI_FREE(obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum kxcjk1013_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (mode == STANDBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) KXCJK1013_REG_CTRL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enum kxcjk1013_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *mode = OPERATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *mode = STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) KXCJK1013_REG_CTRL1_BIT_GSEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) KXCJK1013_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) data->range = range_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (data->acpi_type == ACPI_KIOX010A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) kiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&data->client->dev, "Error reading who_am_i\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Set 12 bit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret |= KXCJK1013_REG_CTRL1_BIT_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(&data->client->dev, "Error reading reg_ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Setting range to 4G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_DATA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) data->odr_bits = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Set up INT polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (data->active_high_intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int idx = data->chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0; i < ARRAY_SIZE(odr_start_up_times[idx]); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (odr_start_up_times[idx][i].odr_bits == data->odr_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return odr_start_up_times[idx][i].usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return KXCJK1013_MAX_STARTUP_TIME_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = pm_runtime_get_sync(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pm_runtime_mark_last_busy(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = pm_runtime_put_autosuspend(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "Failed: %s for %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pm_runtime_put_noidle(&data->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int waketh_reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) KXCJK1013_REG_WAKE_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) data->wake_dur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "Error writing reg_wake_timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) waketh_reg = data->chipset == KXTF9 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) KXTF9_REG_WAKE_THRESH : KXCJK1013_REG_WAKE_THRES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = i2c_smbus_write_byte_data(data->client, waketh_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) data->wake_thres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bool status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) enum kxcjk1013_mode store_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = kxcjk1013_get_mode(data, &store_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* This is requirement by spec to change state to STANDBY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = kxcjk1013_chip_update_thresholds(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) KXCJK1013_REG_CTRL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (store_mode == OPERATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) bool status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) enum kxcjk1013_mode store_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = kxcjk1013_get_mode(data, &store_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* This is requirement by spec to change state to STANDBY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) KXCJK1013_REG_CTRL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (store_mode == OPERATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct kx_odr_map *kxcjk1013_find_odr_value(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const struct kx_odr_map *map, size_t map_size, int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) for (i = 0; i < map_size; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (map[i].val == val && map[i].val2 == val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return &map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) size_t map_size, int odr_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for (i = 0; i < map_size; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (map[i].odr_bits == odr_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *val = map[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *val2 = map[i].val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) enum kxcjk1013_mode store_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) const struct kx_odr_map *odr_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = kxcjk1013_get_mode(data, &store_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (data->chipset == KXTF9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ARRAY_SIZE(kxtf9_samp_freq_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ARRAY_SIZE(samp_freq_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (IS_ERR(odr_setting))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return PTR_ERR(odr_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* To change ODR, the chip must be set to STANDBY as per spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) odr_setting->odr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev_err(&data->client->dev, "Error writing data_ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) data->odr_bits = odr_setting->odr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) odr_setting->wuf_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (store_mode == OPERATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (data->chipset == KXTF9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ARRAY_SIZE(kxtf9_samp_freq_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) data->odr_bits, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return kxcjk1013_convert_odr_value(samp_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ARRAY_SIZE(samp_freq_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) data->odr_bits, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = i2c_smbus_read_word_data(data->client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "failed to read accel_%c registers\n", 'x' + axis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) enum kxcjk1013_mode store_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (KXCJK1013_scale_table[i].scale == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = kxcjk1013_get_mode(data, &store_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = kxcjk1013_set_range(data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (store_mode == OPERATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct iio_chan_spec const *chan, int *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (iio_buffer_enabled(indio_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = kxcjk1013_set_power_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) kxcjk1013_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) *val = sign_extend32(ret >> 4, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = kxcjk1013_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *val2 = KXCJK1013_scale_table[data->range].scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = kxcjk1013_get_odr(data, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct iio_chan_spec const *chan, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) case IIO_CHAN_INFO_SAMP_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = kxcjk1013_set_odr(data, val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = kxcjk1013_set_scale(data, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int kxcjk1013_read_event(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int *val, int *val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) *val2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *val = data->wake_thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) *val = data->wake_dur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int kxcjk1013_write_event(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) enum iio_event_info info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int val, int val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (data->ev_enable_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) switch (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case IIO_EV_INFO_VALUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) data->wake_thres = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case IIO_EV_INFO_PERIOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) data->wake_dur = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) enum iio_event_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return data->ev_enable_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) const struct iio_chan_spec *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) enum iio_event_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) enum iio_event_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (state && data->ev_enable_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!state && data->motion_trigger_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) data->ev_enable_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * We will expect the enable and disable to do operation in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * in reverse order. This will happen here anyway as our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * resume operation uses sync mode runtime pm calls, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * suspend operation will be delayed by autosuspend delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * So the disable operation will still happen in reverse of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * enable operation. When runtime pm is disabled the mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * is always on so sequence doesn't matter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = kxcjk1013_set_power_state(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = kxcjk1013_setup_any_motion_interrupt(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) kxcjk1013_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) data->ev_enable_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) data->ev_enable_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return kxcjk1013_set_power_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return kxcjk1013_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct iio_dev *indio_dev = dev_to_iio_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) const char *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (data->chipset == KXTF9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) str = kxtf9_samp_freq_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) str = kxcjk1013_samp_freq_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return sprintf(buf, "%s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) kxcjk1013_get_samp_freq_avail, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static struct attribute *kxcjk1013_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) &iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) &iio_const_attr_in_accel_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const struct attribute_group kxcjk1013_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .attrs = kxcjk1013_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const struct iio_event_spec kxcjk1013_event = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .type = IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .dir = IIO_EV_DIR_EITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .mask_separate = BIT(IIO_EV_INFO_VALUE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) BIT(IIO_EV_INFO_ENABLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) BIT(IIO_EV_INFO_PERIOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static const struct iio_mount_matrix *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) kxcjk1013_get_mount_matrix(const struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return &data->orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const struct iio_chan_spec_ext_info kxcjk1013_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxcjk1013_get_mount_matrix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define KXCJK1013_CHANNEL(_axis) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .channel2 = IIO_MOD_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) BIT(IIO_CHAN_INFO_SAMP_FREQ), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .scan_index = AXIS_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .realbits = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .shift = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .endianness = IIO_LE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .event_spec = &kxcjk1013_event, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .ext_info = kxcjk1013_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .num_event_specs = 1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct iio_chan_spec kxcjk1013_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) KXCJK1013_CHANNEL(X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) KXCJK1013_CHANNEL(Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) KXCJK1013_CHANNEL(Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) IIO_CHAN_SOFT_TIMESTAMP(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .preenable = kxcjk1013_buffer_preenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .postdisable = kxcjk1013_buffer_postdisable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const struct iio_info kxcjk1013_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .attrs = &kxcjk1013_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .read_raw = kxcjk1013_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .write_raw = kxcjk1013_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .read_event_value = kxcjk1013_read_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .write_event_value = kxcjk1013_write_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .write_event_config = kxcjk1013_write_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .read_event_config = kxcjk1013_read_event_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = i2c_smbus_read_i2c_block_data_or_emulated(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) KXCJK1013_REG_XOUT_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) AXIS_MAX * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) (u8 *)data->scan.chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int kxcjk1013_trig_try_reen(struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dev_err(&data->client->dev, "Error reading reg_int_rel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!state && data->ev_enable_state && data->motion_trigger_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) data->motion_trigger_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ret = kxcjk1013_set_power_state(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (data->motion_trig == trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ret = kxcjk1013_setup_any_motion_interrupt(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ret = kxcjk1013_setup_new_data_interrupt(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) kxcjk1013_set_power_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (data->motion_trig == trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) data->motion_trigger_on = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) data->dready_trigger_on = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .try_reenable = kxcjk1013_trig_try_reen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int ret = i2c_smbus_read_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) KXCJK1013_REG_INT_SRC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dev_err(&data->client->dev, "Error reading reg_int_src2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) IIO_MOD_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) IIO_MOD_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) IIO_MOD_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) IIO_MOD_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) IIO_MOD_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) IIO_EV_DIR_FALLING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) IIO_MOD_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_SRC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_err(&data->client->dev, "Error reading reg_int_src1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) goto ack_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (data->chipset == KXTF9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) iio_push_event(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) IIO_MOD_EVENT_CODE(IIO_ACCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) IIO_MOD_X_AND_Y_AND_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) IIO_EV_TYPE_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) IIO_EV_DIR_RISING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) data->timestamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) kxcjk1013_report_motion_event(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ack_intr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (data->dready_trigger_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) dev_err(&data->client->dev, "Error reading reg_int_rel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct iio_dev *indio_dev = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) data->timestamp = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (data->dready_trigger_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) iio_trigger_poll(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) else if (data->motion_trigger_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) iio_trigger_poll(data->motion_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (data->ev_enable_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const char *kxcjk1013_match_acpi_device(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) enum kx_chipset *chipset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) enum kx_acpi_type *acpi_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) const struct acpi_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) id = acpi_match_device(dev->driver->acpi_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (strcmp(id->id, "SMO8500") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) *acpi_type = ACPI_SMO8500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) else if (strcmp(id->id, "KIOX010A") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) *acpi_type = ACPI_KIOX010A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) *chipset = (enum kx_chipset)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int kxcjk1013_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct kxcjk1013_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct kxcjk_1013_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) data->active_high_intr = pdata->active_high_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) data->orientation = pdata->orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) data->active_high_intr = true; /* default polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = iio_read_mount_matrix(&client->dev, "mount-matrix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) &data->orientation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) data->chipset = (enum kx_chipset)(id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) } else if (ACPI_HANDLE(&client->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) name = kxcjk1013_match_acpi_device(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) &data->chipset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) &data->acpi_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = kxcjk1013_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) indio_dev->channels = kxcjk1013_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) indio_dev->available_scan_masks = kxcjk1013_scan_masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) indio_dev->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) indio_dev->info = &kxcjk1013_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (client->irq > 0 && data->acpi_type != ACPI_SMO8500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) kxcjk1013_data_rdy_trig_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) kxcjk1013_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) KXCJK1013_IRQ_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) goto err_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) data->dready_trig = devm_iio_trigger_alloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) "%s-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!data->dready_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) goto err_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) data->motion_trig = devm_iio_trigger_alloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) "%s-any-motion-dev%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (!data->motion_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) goto err_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) data->dready_trig->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) data->dready_trig->ops = &kxcjk1013_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) iio_trigger_set_drvdata(data->dready_trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) indio_dev->trig = data->dready_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) iio_trigger_get(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = iio_trigger_register(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) goto err_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) data->motion_trig->dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) data->motion_trig->ops = &kxcjk1013_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) iio_trigger_set_drvdata(data->motion_trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ret = iio_trigger_register(data->motion_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) data->motion_trig = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) goto err_trigger_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ret = iio_triggered_buffer_setup(indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) &iio_pollfunc_store_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) kxcjk1013_trigger_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) &kxcjk1013_buffer_setup_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dev_err(&client->dev, "iio triggered buffer setup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) goto err_trigger_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) goto err_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) pm_runtime_set_autosuspend_delay(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) KXCJK1013_SLEEP_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) pm_runtime_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_err(&client->dev, "unable to register iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) goto err_pm_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) err_pm_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) pm_runtime_dont_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) err_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) err_trigger_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (data->dready_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) iio_trigger_unregister(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (data->motion_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) iio_trigger_unregister(data->motion_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) err_poweroff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static int kxcjk1013_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (data->dready_trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) iio_trigger_unregister(data->dready_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) iio_trigger_unregister(data->motion_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static int kxcjk1013_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static int kxcjk1013_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret = kxcjk1013_set_range(data, data->range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static int kxcjk1013_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) ret = kxcjk1013_set_mode(data, STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) dev_err(&data->client->dev, "powering off device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int kxcjk1013_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct kxcjk1013_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int sleep_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = kxcjk1013_set_mode(data, OPERATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) sleep_val = kxcjk1013_get_startup_times(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (sleep_val < 20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) usleep_range(sleep_val, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) msleep_interruptible(sleep_val/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const struct dev_pm_ops kxcjk1013_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) SET_SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SET_RUNTIME_PM_OPS(kxcjk1013_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) kxcjk1013_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static const struct acpi_device_id kx_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {"KXCJ1013", KXCJK1013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {"KXCJ1008", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {"KXCJ9000", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {"KIOX0008", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {"KIOX0009", KXTJ21009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {"KIOX000A", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {"KIOX010A", KXCJ91008}, /* KXCJ91008 in the display of a yoga 2-in-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {"KIOX020A", KXCJ91008}, /* KXCJ91008 in the base of a yoga 2-in-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {"KXTJ1009", KXTJ21009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {"KXJ2109", KXTJ21009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {"SMO8500", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct i2c_device_id kxcjk1013_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {"kxcjk1013", KXCJK1013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {"kxcj91008", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {"kxtj21009", KXTJ21009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) {"kxtf9", KXTF9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {"SMO8500", KXCJ91008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static const struct of_device_id kxcjk1013_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) { .compatible = "kionix,kxcjk1013", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) { .compatible = "kionix,kxcj91008", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) { .compatible = "kionix,kxtj21009", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) { .compatible = "kionix,kxtf9", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) MODULE_DEVICE_TABLE(of, kxcjk1013_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static struct i2c_driver kxcjk1013_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .name = KXCJK1013_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .acpi_match_table = ACPI_PTR(kx_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .of_match_table = kxcjk1013_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .pm = &kxcjk1013_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .probe = kxcjk1013_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .remove = kxcjk1013_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .id_table = kxcjk1013_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) module_i2c_driver(kxcjk1013_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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