Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * IIO driver for the 3-axis accelerometer Domintech ARD10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2012 Domintech Technology Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/byteorder/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DMARD10_REG_ACTR			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DMARD10_REG_AFEM			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DMARD10_REG_STADR			0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DMARD10_REG_STAINT			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DMARD10_REG_MISC2			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DMARD10_REG_PD				0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DMARD10_MODE_OFF			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DMARD10_MODE_STANDBY			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DMARD10_MODE_ACTIVE			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DMARD10_MODE_READ_OTP			0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DMARD10_MODE_RESET_DATA_PATH		0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* AFEN set 1, ATM[2:0]=b'000 (normal), EN_Z/Y/X/T=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DMARD10_VALUE_AFEM_AFEN_NORMAL		0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* ODR[3:0]=b'0111 (100Hz), CCK[3:0]=b'0100 (204.8kHZ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DMARD10_VALUE_CKSEL_ODR_100_204		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* INTC[6:5]=b'00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DMARD10_VALUE_INTC			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* TAP1/TAP2 Average 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DMARD10_VALUE_TAPNS_AVE_2		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DMARD10_VALUE_STADR			0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DMARD10_VALUE_STAINT			0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DMARD10_VALUE_MISC2_OSCA_EN		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DMARD10_VALUE_PD_RST			0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Offsets into the buffer read in dmard10_read_raw() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DMARD10_X_OFFSET			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DMARD10_Y_OFFSET			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DMARD10_Z_OFFSET			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * a value of + or -128 corresponds to + or - 1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * scale = 9.81 / 128 = 0.076640625
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const int dmard10_nscale = 76640625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DMARD10_CHANNEL(reg, axis) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.type = IIO_ACCEL,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.address = reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.modified = 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.channel2 = IIO_MOD_##axis,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct iio_chan_spec dmard10_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	DMARD10_CHANNEL(DMARD10_X_OFFSET, X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	DMARD10_CHANNEL(DMARD10_Y_OFFSET, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	DMARD10_CHANNEL(DMARD10_Z_OFFSET, Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct dmard10_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Init sequence taken from the android driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int dmard10_reset(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned char buffer[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* 1. Powerdown reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	ret = i2c_smbus_write_byte_data(client, DMARD10_REG_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 						DMARD10_VALUE_PD_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * 2. ACTR => Standby mode => Download OTP to parameter reg =>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 *    Standby mode => Reset data path => Standby mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	buffer[0] = DMARD10_REG_ACTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	buffer[1] = DMARD10_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	buffer[2] = DMARD10_MODE_READ_OTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	buffer[3] = DMARD10_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	buffer[4] = DMARD10_MODE_RESET_DATA_PATH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	buffer[5] = DMARD10_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	ret = i2c_master_send(client, buffer, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* 3. OSCA_EN = 1, TSTO = b'000 (INT1 = normal, TEST0 = normal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ret = i2c_smbus_write_byte_data(client, DMARD10_REG_MISC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 						DMARD10_VALUE_MISC2_OSCA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* 4. AFEN = 1 (AFE will powerdown after ADC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	buffer[0] = DMARD10_REG_AFEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	buffer[1] = DMARD10_VALUE_AFEM_AFEN_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	buffer[2] = DMARD10_VALUE_CKSEL_ODR_100_204;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	buffer[3] = DMARD10_VALUE_INTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	buffer[4] = DMARD10_VALUE_TAPNS_AVE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	buffer[5] = 0x00; /* DLYC, no delay timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	buffer[6] = 0x07; /* INTD=1 push-pull, INTA=1 active high, AUTOT=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = i2c_master_send(client, buffer, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* 5. Activation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ret = i2c_smbus_write_byte_data(client, DMARD10_REG_ACTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 						DMARD10_MODE_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Shutdown sequence taken from the android driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int dmard10_shutdown(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned char buffer[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	buffer[0] = DMARD10_REG_ACTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	buffer[1] = DMARD10_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	buffer[2] = DMARD10_MODE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return i2c_master_send(client, buffer, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int dmard10_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 				int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct dmard10_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__le16 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		 * Read 8 bytes starting at the REG_STADR register, trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		 * read the individual X, Y, Z registers will always read 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 						    DMARD10_REG_STADR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 						    sizeof(buf), (u8 *)buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		ret = le16_to_cpu(buf[chan->address]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		*val = sign_extend32(ret, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		*val2 = dmard10_nscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct iio_info dmard10_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.read_raw	= dmard10_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int dmard10_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct dmard10_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* These 2 registers have special POR reset values used for id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = i2c_smbus_read_byte_data(client, DMARD10_REG_STADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret != DMARD10_VALUE_STADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return (ret < 0) ? ret : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = i2c_smbus_read_byte_data(client, DMARD10_REG_STAINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret != DMARD10_VALUE_STAINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return (ret < 0) ? ret : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		dev_err(&client->dev, "iio allocation failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	indio_dev->info = &dmard10_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	indio_dev->name = "dmard10";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	indio_dev->channels = dmard10_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	indio_dev->num_channels = ARRAY_SIZE(dmard10_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ret = dmard10_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		dev_err(&client->dev, "device_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		dmard10_shutdown(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int dmard10_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return dmard10_shutdown(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int dmard10_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return dmard10_shutdown(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int dmard10_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return dmard10_reset(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static SIMPLE_DEV_PM_OPS(dmard10_pm_ops, dmard10_suspend, dmard10_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct i2c_device_id dmard10_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	{"dmard10", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DEVICE_TABLE(i2c, dmard10_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct i2c_driver dmard10_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.name = "dmard10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.pm = &dmard10_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.probe		= dmard10_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.remove		= dmard10_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.id_table	= dmard10_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) module_i2c_driver(dmard10_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MODULE_DESCRIPTION("Domintech ARD10 3-Axis Accelerometer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_LICENSE("GPL v2");