^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IIO driver for the 3-axis accelerometer Domintech DMARD09.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016, Jelle van der Waa <jelle@vdwaa.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DMARD09_DRV_NAME "dmard09"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DMARD09_REG_CHIPID 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DMARD09_REG_STAT 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DMARD09_REG_X 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMARD09_REG_Y 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMARD09_REG_Z 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMARD09_CHIPID 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DMARD09_BUF_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMARD09_AXIS_X 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMARD09_AXIS_Y 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMARD09_AXIS_Z 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMARD09_AXIS_X_OFFSET ((DMARD09_AXIS_X + 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMARD09_AXIS_Y_OFFSET ((DMARD09_AXIS_Y + 1 )* 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMARD09_AXIS_Z_OFFSET ((DMARD09_AXIS_Z + 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct dmard09_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMARD09_CHANNEL(_axis, offset) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .address = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .channel2 = IIO_MOD_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct iio_chan_spec dmard09_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DMARD09_CHANNEL(X, DMARD09_AXIS_X_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DMARD09_CHANNEL(Y, DMARD09_AXIS_Y_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DMARD09_CHANNEL(Z, DMARD09_AXIS_Z_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int dmard09_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dmard09_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 buf[DMARD09_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) s16 accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Read from the DMAR09_REG_STAT register, since the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * caches reads from the individual X, Y, Z registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = i2c_smbus_read_i2c_block_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DMARD09_REG_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DMARD09_BUF_LEN, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev_err(&data->client->dev, "Error reading reg %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DMARD09_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) accel = get_unaligned_le16(&buf[chan->address]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Remove lower 3 bits and sign extend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) accel <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) accel >>= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *val = accel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct iio_info dmard09_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .read_raw = dmard09_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int dmard09_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct dmard09_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_err(&client->dev, "iio allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = i2c_smbus_read_byte_data(data->client, DMARD09_REG_CHIPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(&client->dev, "Error reading chip id %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret != DMARD09_CHIPID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(&client->dev, "Invalid chip id %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) indio_dev->name = DMARD09_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) indio_dev->channels = dmard09_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) indio_dev->num_channels = ARRAY_SIZE(dmard09_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) indio_dev->info = &dmard09_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct i2c_device_id dmard09_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { "dmard09", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MODULE_DEVICE_TABLE(i2c, dmard09_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct i2c_driver dmard09_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = DMARD09_DRV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .probe = dmard09_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .id_table = dmard09_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) module_i2c_driver(dmard09_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODULE_AUTHOR("Jelle van der Waa <jelle@vdwaa.nl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MODULE_DESCRIPTION("DMARD09 3-axis accelerometer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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