^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IIO driver for Domintech DMARD06 accelerometer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Aleksei Mamlin <mamlinav@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DMARD06_DRV_NAME "dmard06"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Device data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DMARD06_CHIP_ID_REG 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DMARD06_TOUT_REG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMARD06_XOUT_REG 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMARD06_YOUT_REG 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMARD06_ZOUT_REG 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMARD06_CTRL1_REG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Device ID value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMARD05_CHIP_ID 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMARD06_CHIP_ID 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMARD07_CHIP_ID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Device values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMARD05_AXIS_SCALE_VAL 15625
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DMARD06_AXIS_SCALE_VAL 31250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DMARD06_TEMP_CENTER_VAL 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DMARD06_SIGN_BIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Device power modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMARD06_MODE_NORMAL 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMARD06_MODE_POWERDOWN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Device channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMARD06_ACCEL_CHANNEL(_axis, _reg) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .address = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .channel2 = IIO_MOD_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DMARD06_TEMP_CHANNEL(_reg) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .type = IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .address = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct dmard06_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct iio_chan_spec dmard06_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DMARD06_ACCEL_CHANNEL(X, DMARD06_XOUT_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DMARD06_ACCEL_CHANNEL(Y, DMARD06_YOUT_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DMARD06_ACCEL_CHANNEL(Z, DMARD06_ZOUT_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DMARD06_TEMP_CHANNEL(DMARD06_TOUT_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int dmard06_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct dmard06_data *dmard06 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = i2c_smbus_read_byte_data(dmard06->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dev_err(&dmard06->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "Error reading data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *val = sign_extend32(ret, DMARD06_SIGN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (dmard06->chip_id == DMARD06_CHIP_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *val = *val >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (dmard06->chip_id != DMARD06_CHIP_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *val = *val / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *val = DMARD06_TEMP_CENTER_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (dmard06->chip_id == DMARD06_CHIP_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *val2 = DMARD06_AXIS_SCALE_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *val2 = DMARD05_AXIS_SCALE_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct iio_info dmard06_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .read_raw = dmard06_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int dmard06_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dmard06_data *dmard06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(&client->dev, "I2C check functionality failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*dmard06));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!indio_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(&client->dev, "Failed to allocate iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dmard06 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dmard06->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = i2c_smbus_read_byte_data(dmard06->client, DMARD06_CHIP_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(&client->dev, "Error reading chip id: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret != DMARD05_CHIP_ID && ret != DMARD06_CHIP_ID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret != DMARD07_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(&client->dev, "Invalid chip id: %02d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dmard06->chip_id = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) indio_dev->name = DMARD06_DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) indio_dev->channels = dmard06_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) indio_dev->num_channels = ARRAY_SIZE(dmard06_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) indio_dev->info = &dmard06_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return devm_iio_device_register(&client->dev, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int dmard06_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct dmard06_data *dmard06 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = i2c_smbus_write_byte_data(dmard06->client, DMARD06_CTRL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DMARD06_MODE_POWERDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int dmard06_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dmard06_data *dmard06 = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = i2c_smbus_write_byte_data(dmard06->client, DMARD06_CTRL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DMARD06_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static SIMPLE_DEV_PM_OPS(dmard06_pm_ops, dmard06_suspend, dmard06_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DMARD06_PM_OPS (&dmard06_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DMARD06_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct i2c_device_id dmard06_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { "dmard05", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { "dmard06", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { "dmard07", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_DEVICE_TABLE(i2c, dmard06_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct of_device_id dmard06_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .compatible = "domintech,dmard05" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .compatible = "domintech,dmard06" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { .compatible = "domintech,dmard07" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_DEVICE_TABLE(of, dmard06_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct i2c_driver dmard06_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .probe = dmard06_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .id_table = dmard06_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .name = DMARD06_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .of_match_table = dmard06_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .pm = DMARD06_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) module_i2c_driver(dmard06_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_AUTHOR("Aleksei Mamlin <mamlinav@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DESCRIPTION("Domintech DMARD06 accelerometer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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