Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * IIO driver for the MiraMEMS DA311 3-axis accelerometer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2011-2013 MiraMEMS Sensing Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/byteorder/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DA311_CHIP_ID			0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Note register addressed go from 0 - 0x3f and then wrap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * For some reason there are 2 banks with 0 - 0x3f addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * rather then a single 0-0x7f bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* Bank 0 regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DA311_REG_BANK			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DA311_REG_LDO_REG		0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DA311_REG_CHIP_ID		0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DA311_REG_TEMP_CFG_REG		0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DA311_REG_CTRL_REG1		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DA311_REG_CTRL_REG3		0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DA311_REG_CTRL_REG4		0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DA311_REG_CTRL_REG5		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DA311_REG_CTRL_REG6		0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DA311_REG_STATUS_REG		0x0027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DA311_REG_OUT_X_L		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DA311_REG_OUT_X_H		0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DA311_REG_OUT_Y_L		0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DA311_REG_OUT_Y_H		0x002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DA311_REG_OUT_Z_L		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DA311_REG_OUT_Z_H		0x002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DA311_REG_INT1_CFG		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DA311_REG_INT1_SRC		0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DA311_REG_INT1_THS		0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DA311_REG_INT1_DURATION		0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DA311_REG_INT2_CFG		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DA311_REG_INT2_SRC		0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DA311_REG_INT2_THS		0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DA311_REG_INT2_DURATION		0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DA311_REG_CLICK_CFG		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DA311_REG_CLICK_SRC		0x0039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DA311_REG_CLICK_THS		0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DA311_REG_TIME_LIMIT		0x003b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DA311_REG_TIME_LATENCY		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DA311_REG_TIME_WINDOW		0x003d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Bank 1 regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DA311_REG_SOFT_RESET		0x0105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DA311_REG_OTP_XOFF_L		0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DA311_REG_OTP_XOFF_H		0x0111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DA311_REG_OTP_YOFF_L		0x0112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DA311_REG_OTP_YOFF_H		0x0113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DA311_REG_OTP_ZOFF_L		0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DA311_REG_OTP_ZOFF_H		0x0115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DA311_REG_OTP_XSO		0x0116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DA311_REG_OTP_YSO		0x0117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DA311_REG_OTP_ZSO		0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DA311_REG_OTP_TRIM_OSC		0x011b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DA311_REG_LPF_ABSOLUTE		0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DA311_REG_TEMP_OFF1		0x0127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DA311_REG_TEMP_OFF2		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DA311_REG_TEMP_OFF3		0x0129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DA311_REG_OTP_TRIM_THERM_H	0x011a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * a value of + or -1024 corresponds to + or - 1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * scale = 9.81 / 1024 = 0.009580078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static const int da311_nscale = 9580078;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DA311_CHANNEL(reg, axis) {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.type = IIO_ACCEL,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.address = reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.modified = 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.channel2 = IIO_MOD_##axis,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static const struct iio_chan_spec da311_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* | 0x80 comes from the android driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	DA311_CHANNEL(DA311_REG_OUT_X_L | 0x80, X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	DA311_CHANNEL(DA311_REG_OUT_Y_L | 0x80, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	DA311_CHANNEL(DA311_REG_OUT_Z_L | 0x80, Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct da311_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int da311_register_mask_write(struct i2c_client *client, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				     u8 mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 tmp_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (addr & 0xff00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		/* Select bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		ret = i2c_smbus_write_byte_data(client, DA311_REG_BANK, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (mask != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		ret = i2c_smbus_read_byte_data(client, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		tmp_data = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tmp_data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	tmp_data |= data & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	ret = i2c_smbus_write_byte_data(client, addr & 0xff, tmp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (addr & 0xff00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		/* Back to bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		ret = i2c_smbus_write_byte_data(client, DA311_REG_BANK, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Init sequence taken from the android driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int da311_reset(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	} init_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		{ DA311_REG_TEMP_CFG_REG,       0xff,   0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		{ DA311_REG_CTRL_REG5,          0xff,   0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		{ DA311_REG_CTRL_REG4,          0x30,   0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		{ DA311_REG_CTRL_REG1,          0xff,   0x6f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		{ DA311_REG_TEMP_CFG_REG,       0xff,   0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		{ DA311_REG_LDO_REG,            0xff,   0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		{ DA311_REG_OTP_TRIM_OSC,       0xff,   0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		{ DA311_REG_LPF_ABSOLUTE,       0xff,   0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		{ DA311_REG_TEMP_OFF1,          0xff,   0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		{ DA311_REG_TEMP_OFF2,          0xff,   0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		{ DA311_REG_TEMP_OFF3,          0xff,   0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ret = da311_register_mask_write(client, DA311_REG_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					0xff, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	for (i = 0; i < ARRAY_SIZE(init_data); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		ret = da311_register_mask_write(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 						init_data[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 						init_data[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 						init_data[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int da311_enable(struct i2c_client *client, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u8 data = enable ? 0x00 : 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return da311_register_mask_write(client, DA311_REG_TEMP_CFG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 					 0x20, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int da311_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				struct iio_chan_spec const *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				int *val, int *val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct da311_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ret = i2c_smbus_read_word_data(data->client, chan->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		 * Values are 12 bits, stored as 16 bits with the 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		 * least significant bits always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		*val = (short)ret >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		*val2 = da311_nscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return IIO_VAL_INT_PLUS_NANO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct iio_info da311_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.read_raw	= da311_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int da311_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct da311_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	ret = i2c_smbus_read_byte_data(client, DA311_REG_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (ret != DA311_CHIP_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return (ret < 0) ? ret : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	indio_dev->info = &da311_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	indio_dev->name = "da311";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	indio_dev->channels = da311_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	indio_dev->num_channels = ARRAY_SIZE(da311_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	ret = da311_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	ret = da311_enable(client, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		dev_err(&client->dev, "device_register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		da311_enable(client, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int da311_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return da311_enable(client, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int da311_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return da311_enable(to_i2c_client(dev), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int da311_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	return da311_enable(to_i2c_client(dev), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static SIMPLE_DEV_PM_OPS(da311_pm_ops, da311_suspend, da311_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct i2c_device_id da311_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{"da311", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_DEVICE_TABLE(i2c, da311_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct i2c_driver da311_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.name = "da311",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.pm = &da311_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.probe		= da311_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.remove		= da311_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.id_table	= da311_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) module_i2c_driver(da311_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_DESCRIPTION("MiraMEMS DA311 3-Axis Accelerometer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_LICENSE("GPL v2");