Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Register constants and other forward declarations needed by the bma400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright 2019 Dan Robertson <dan@dlrobertson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _BMA400_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _BMA400_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * Read-Only Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Status and ID registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BMA400_CHIP_ID_REG          0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BMA400_ERR_REG              0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BMA400_STATUS_REG           0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Acceleration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BMA400_X_AXIS_LSB_REG       0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BMA400_X_AXIS_MSB_REG       0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BMA400_Y_AXIS_LSB_REG       0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BMA400_Y_AXIS_MSB_REG       0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BMA400_Z_AXIS_LSB_REG       0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BMA400_Z_AXIS_MSB_REG       0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Sensor time registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BMA400_SENSOR_TIME0         0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BMA400_SENSOR_TIME1         0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BMA400_SENSOR_TIME2         0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Event and interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BMA400_EVENT_REG            0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BMA400_INT_STAT0_REG        0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BMA400_INT_STAT1_REG        0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BMA400_INT_STAT2_REG        0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Temperature register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BMA400_TEMP_DATA_REG        0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* FIFO length and data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BMA400_FIFO_LENGTH0_REG     0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BMA400_FIFO_LENGTH1_REG     0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BMA400_FIFO_DATA_REG        0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Step count registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BMA400_STEP_CNT0_REG        0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BMA400_STEP_CNT1_REG        0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BMA400_STEP_CNT3_REG        0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BMA400_STEP_STAT_REG        0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  * Read-write configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BMA400_ACC_CONFIG0_REG      0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BMA400_ACC_CONFIG1_REG      0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BMA400_ACC_CONFIG2_REG      0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BMA400_CMD_REG              0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Chip ID of BMA 400 devices found in the chip ID register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BMA400_ID_REG_VAL           0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BMA400_LP_OSR_SHIFT         5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BMA400_NP_OSR_SHIFT         4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BMA400_SCALE_SHIFT          6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BMA400_TWO_BITS_MASK        GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BMA400_LP_OSR_MASK          GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BMA400_NP_OSR_MASK          GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BMA400_ACC_ODR_MASK         GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BMA400_ACC_SCALE_MASK       GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BMA400_ACC_ODR_MIN_RAW      0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BMA400_ACC_ODR_LP_RAW       0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BMA400_ACC_ODR_MAX_RAW      0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BMA400_ACC_ODR_MAX_HZ       800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BMA400_ACC_ODR_MIN_WHOLE_HZ 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BMA400_ACC_ODR_MIN_HZ       12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BMA400_SCALE_MIN            38357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BMA400_SCALE_MAX            306864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BMA400_NUM_REGULATORS       2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BMA400_VDD_REGULATOR        0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BMA400_VDDIO_REGULATOR      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern const struct regmap_config bma400_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int bma400_probe(struct device *dev, struct regmap *regmap, const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int bma400_remove(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif