^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bma180.c - IIO driver for Bosch BMA180 triaxial acceleration sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Oleksandr Kravchenko <x0199363@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Support for BMA250 (c) Peter Meerwald <pmeerw@pmeerw.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * SPI is not supported by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * BMA023/BMA150/SMB380: 7-bit I2C slave address 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * BMA180: 7-bit I2C slave address 0x40 or 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * BMA250: 7-bit I2C slave address 0x18 or 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * BMA254: 7-bit I2C slave address 0x18 or 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iio/iio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/iio/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/iio/buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/iio/trigger.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/iio/trigger_consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/iio/triggered_buffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BMA180_DRV_NAME "bma180"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BMA180_IRQ_NAME "bma180_event"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum chip_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BMA023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) BMA150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) BMA180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) BMA250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) BMA254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct bma180_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct bma180_part_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct iio_chan_spec *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const int *scale_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int num_scales;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const int *bw_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int num_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 int_reset_reg, int_reset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 sleep_reg, sleep_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 bw_reg, bw_mask, bw_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 scale_reg, scale_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 power_reg, power_mask, lowpower_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 int_enable_reg, int_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 int_map_reg, int_enable_dataready_int1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 softreset_reg, softreset_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int (*chip_config)(struct bma180_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void (*chip_disable)(struct bma180_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BMA023_CTRL_REG0 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BMA023_CTRL_REG1 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BMA023_CTRL_REG2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BMA023_CTRL_REG3 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BMA023_RANGE_MASK GENMASK(4, 3) /* Range of accel values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BMA023_BW_MASK GENMASK(2, 0) /* Accel bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BMA023_SLEEP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BMA023_INT_RESET_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BMA023_NEW_DATA_INT BIT(5) /* Intr every new accel data is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BMA023_RESET_VAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BMA180_CHIP_ID 0x00 /* Need to distinguish BMA180 from other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BMA180_ACC_X_LSB 0x02 /* First of 6 registers of accel data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BMA180_TEMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BMA180_CTRL_REG0 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BMA180_RESET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BMA180_BW_TCS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BMA180_CTRL_REG3 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BMA180_TCO_Z 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BMA180_OFFSET_LSB1 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* BMA180_CTRL_REG0 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BMA180_DIS_WAKE_UP BIT(0) /* Disable wake up mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BMA180_SLEEP BIT(1) /* 1 - chip will sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BMA180_EE_W BIT(4) /* Unlock writing to addr from 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BMA180_RESET_INT BIT(6) /* Reset pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* BMA180_CTRL_REG3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BMA180_NEW_DATA_INT BIT(1) /* Intr every new accel data is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* BMA180_OFFSET_LSB1 skipping mode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BMA180_SMP_SKIP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Bit masks for registers bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BMA180_RANGE 0x0e /* Range of measured accel values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BMA180_BW 0xf0 /* Accel bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BMA180_MODE_CONFIG 0x03 /* Config operation modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* We have to write this value in reset register to do soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BMA180_RESET_VAL 0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BMA023_ID_REG_VAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BMA180_ID_REG_VAL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BMA250_ID_REG_VAL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BMA254_ID_REG_VAL 0xfa /* 250 decimal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Chip power modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BMA180_LOW_POWER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BMA250_RANGE_REG 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BMA250_BW_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BMA250_POWER_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BMA250_RESET_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BMA250_INT_ENABLE_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BMA250_INT_MAP_REG 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BMA250_INT_RESET_REG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BMA250_RANGE_MASK GENMASK(3, 0) /* Range of accel values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BMA250_BW_MASK GENMASK(4, 0) /* Accel bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BMA250_BW_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BMA250_SUSPEND_MASK BIT(7) /* chip will sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BMA250_LOWPOWER_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BMA250_DATA_INTEN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BMA250_INT1_DATA_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BMA250_INT_RESET_MASK BIT(7) /* Reset pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BMA254_RANGE_REG 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BMA254_BW_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BMA254_POWER_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BMA254_RESET_REG 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BMA254_INT_ENABLE_REG 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BMA254_INT_MAP_REG 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BMA254_INT_RESET_REG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BMA254_RANGE_MASK GENMASK(3, 0) /* Range of accel values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BMA254_BW_MASK GENMASK(4, 0) /* Accel bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BMA254_BW_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BMA254_SUSPEND_MASK BIT(7) /* chip will sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BMA254_LOWPOWER_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BMA254_DATA_INTEN_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BMA254_INT2_DATA_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BMA254_INT1_DATA_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BMA254_INT_RESET_MASK BIT(7) /* Reset pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct bma180_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct regulator *vdd_supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct regulator *vddio_supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct iio_trigger *trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct bma180_part_info *part_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct iio_mount_matrix orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool sleep_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool pmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Ensure timestamp is naturally aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) s16 chan[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) s64 timestamp __aligned(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } scan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum bma180_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) AXIS_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) AXIS_Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) AXIS_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) TEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int bma023_bw_table[] = { 25, 50, 100, 190, 375, 750, 1500 }; /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int bma023_scale_table[] = { 2452, 4903, 9709, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int bma180_bw_table[] = { 10, 20, 40, 75, 150, 300 }; /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int bma180_scale_table[] = { 1275, 1863, 2452, 3727, 4903, 9709, 19417 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int bma25x_bw_table[] = { 8, 16, 31, 63, 125, 250 }; /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int bma25x_scale_table[] = { 0, 0, 0, 38344, 0, 76590, 0, 0, 153180, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0, 0, 306458 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int bma180_get_data_reg(struct bma180_data *data, enum bma180_chan chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (data->sleep_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) switch (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = i2c_smbus_read_byte_data(data->client, BMA180_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(&data->client->dev, "failed to read temp register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = i2c_smbus_read_word_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) BMA180_ACC_X_LSB + chan * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "failed to read accel_%c register\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 'x' + chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int bma180_set_bits(struct bma180_data *data, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret = i2c_smbus_read_byte_data(data->client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return i2c_smbus_write_byte_data(data->client, reg, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int bma180_reset_intr(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ret = bma180_set_bits(data, data->part_info->int_reset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) data->part_info->int_reset_mask, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(&data->client->dev, "failed to reset interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int bma180_set_new_data_intr_state(struct bma180_data *data, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret = bma180_set_bits(data, data->part_info->int_enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) data->part_info->int_enable_mask, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = bma180_reset_intr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "failed to set new data interrupt state %d\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int bma180_set_sleep_state(struct bma180_data *data, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret = bma180_set_bits(data, data->part_info->sleep_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) data->part_info->sleep_mask, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "failed to set sleep state %d\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) data->sleep_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int bma180_set_ee_writing_state(struct bma180_data *data, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_EE_W, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "failed to set ee writing state %d\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int bma180_set_bw(struct bma180_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (data->sleep_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for (i = 0; i < data->part_info->num_bw; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (data->part_info->bw_table[i] == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = bma180_set_bits(data, data->part_info->bw_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) data->part_info->bw_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) i + data->part_info->bw_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "failed to set bandwidth\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) data->bw = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int bma180_set_scale(struct bma180_data *data, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (data->sleep_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0; i < data->part_info->num_scales; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (data->part_info->scale_table[i] == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = bma180_set_bits(data, data->part_info->scale_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) data->part_info->scale_mask, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(&data->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "failed to set scale\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) data->scale = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int bma180_set_pmode(struct bma180_data *data, bool mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u8 reg_val = mode ? data->part_info->lowpower_val : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ret = bma180_set_bits(data, data->part_info->power_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) data->part_info->power_mask, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(&data->client->dev, "failed to set power mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) data->pmode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int bma180_soft_reset(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ret = i2c_smbus_write_byte_data(data->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data->part_info->softreset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) data->part_info->softreset_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(&data->client->dev, "failed to reset the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int bma180_chip_init(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Try to read chip_id register. It must return 0x03. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret = i2c_smbus_read_byte_data(data->client, BMA180_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ret != data->part_info->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(&data->client->dev, "wrong chip ID %d expected %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret, data->part_info->chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = bma180_soft_reset(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * No serial transaction should occur within minimum 10 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * after soft_reset command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return bma180_set_new_data_intr_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int bma023_chip_config(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret = bma180_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = bma180_set_bw(data, 50); /* 50 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = bma180_set_scale(data, 2452); /* 2 G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&data->client->dev, "failed to config the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int bma180_chip_config(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret = bma180_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = bma180_set_pmode(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_DIS_WAKE_UP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = bma180_set_ee_writing_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = bma180_set_bits(data, BMA180_OFFSET_LSB1, BMA180_SMP_SKIP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = bma180_set_bw(data, 20); /* 20 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = bma180_set_scale(data, 2452); /* 2 G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(&data->client->dev, "failed to config the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int bma25x_chip_config(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ret = bma180_chip_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = bma180_set_pmode(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = bma180_set_bw(data, 16); /* 16 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = bma180_set_scale(data, 38344); /* 2 G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * This enables dataready interrupt on the INT1 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * FIXME: support using the INT2 pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = bma180_set_bits(data, data->part_info->int_map_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) data->part_info->int_enable_dataready_int1_mask, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(&data->client->dev, "failed to config the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void bma023_chip_disable(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (bma180_set_sleep_state(data, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(&data->client->dev, "failed to disable the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void bma180_chip_disable(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (bma180_set_new_data_intr_state(data, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (bma180_set_ee_writing_state(data, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (bma180_set_sleep_state(data, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&data->client->dev, "failed to disable the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void bma25x_chip_disable(struct bma180_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (bma180_set_new_data_intr_state(data, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (bma180_set_sleep_state(data, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(&data->client->dev, "failed to disable the chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static ssize_t bma180_show_avail(char *buf, const int *vals, unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) bool micros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!vals[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) len += scnprintf(buf + len, PAGE_SIZE - len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) micros ? "0.%06d " : "%d ", vals[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) buf[len - 1] = '\n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static ssize_t bma180_show_filter_freq_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct bma180_data *data = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return bma180_show_avail(buf, data->part_info->bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) data->part_info->num_bw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static ssize_t bma180_show_scale_avail(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct bma180_data *data = iio_priv(dev_to_iio_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return bma180_show_avail(buf, data->part_info->scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) data->part_info->num_scales, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) S_IRUGO, bma180_show_filter_freq_avail, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static IIO_DEVICE_ATTR(in_accel_scale_available,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) S_IRUGO, bma180_show_scale_avail, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct attribute *bma180_attributes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct attribute_group bma180_attrs_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .attrs = bma180_attributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int bma180_read_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct iio_chan_spec const *chan, int *val, int *val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case IIO_CHAN_INFO_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = iio_device_claim_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = bma180_get_data_reg(data, chan->scan_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) iio_device_release_direct_mode(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (chan->scan_type.sign == 's') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) *val = sign_extend32(ret >> chan->scan_type.shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) chan->scan_type.realbits - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) *val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *val = data->bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch (chan->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case IIO_ACCEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) *val2 = data->scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return IIO_VAL_INT_PLUS_MICRO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case IIO_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *val = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case IIO_CHAN_INFO_OFFSET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *val = data->part_info->temp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return IIO_VAL_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int bma180_write_raw(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct iio_chan_spec const *chan, int val, int val2, long mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) switch (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case IIO_CHAN_INFO_SCALE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = bma180_set_scale(data, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = bma180_set_bw(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct iio_info bma180_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .attrs = &bma180_attrs_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .read_raw = bma180_read_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .write_raw = bma180_write_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const char * const bma180_power_modes[] = { "low_noise", "low_power" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int bma180_get_power_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return data->pmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int bma180_set_power_mode(struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) const struct iio_chan_spec *chan, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = bma180_set_pmode(data, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const struct iio_mount_matrix *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bma180_accel_get_mount_matrix(const struct iio_dev *indio_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) const struct iio_chan_spec *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return &data->orientation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct iio_enum bma180_power_mode_enum = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .items = bma180_power_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .num_items = ARRAY_SIZE(bma180_power_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .get = bma180_get_power_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .set = bma180_set_power_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const struct iio_chan_spec_ext_info bma023_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma180_accel_get_mount_matrix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const struct iio_chan_spec_ext_info bma180_ext_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) IIO_ENUM("power_mode", IIO_SHARED_BY_TYPE, &bma180_power_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) IIO_ENUM_AVAILABLE("power_mode", &bma180_power_mode_enum),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma180_accel_get_mount_matrix),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define BMA023_ACC_CHANNEL(_axis, _bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .channel2 = IIO_MOD_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .scan_index = AXIS_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .realbits = _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .shift = 16 - _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .ext_info = bma023_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define BMA150_TEMP_CHANNEL { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .type = IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .scan_index = TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .sign = 'u', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .realbits = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define BMA180_ACC_CHANNEL(_axis, _bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .type = IIO_ACCEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .modified = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .channel2 = IIO_MOD_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .scan_index = AXIS_##_axis, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .realbits = _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .shift = 16 - _bits, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .ext_info = bma180_ext_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define BMA180_TEMP_CHANNEL { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .type = IIO_TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .scan_index = TEMP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .scan_type = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .sign = 's', \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .realbits = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .storagebits = 16, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct iio_chan_spec bma023_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) BMA023_ACC_CHANNEL(X, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) BMA023_ACC_CHANNEL(Y, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) BMA023_ACC_CHANNEL(Z, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const struct iio_chan_spec bma150_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) BMA023_ACC_CHANNEL(X, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) BMA023_ACC_CHANNEL(Y, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) BMA023_ACC_CHANNEL(Z, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) BMA150_TEMP_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct iio_chan_spec bma180_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) BMA180_ACC_CHANNEL(X, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) BMA180_ACC_CHANNEL(Y, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) BMA180_ACC_CHANNEL(Z, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) BMA180_TEMP_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const struct iio_chan_spec bma250_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) BMA180_ACC_CHANNEL(X, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) BMA180_ACC_CHANNEL(Y, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) BMA180_ACC_CHANNEL(Z, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) BMA180_TEMP_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const struct iio_chan_spec bma254_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) BMA180_ACC_CHANNEL(X, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) BMA180_ACC_CHANNEL(Y, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BMA180_ACC_CHANNEL(Z, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) BMA180_TEMP_CHANNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) IIO_CHAN_SOFT_TIMESTAMP(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const struct bma180_part_info bma180_part_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [BMA023] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .chip_id = BMA023_ID_REG_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .channels = bma023_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .num_channels = ARRAY_SIZE(bma023_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .scale_table = bma023_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .num_scales = ARRAY_SIZE(bma023_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .bw_table = bma023_bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .num_bw = ARRAY_SIZE(bma023_bw_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* No temperature channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .temp_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .int_reset_reg = BMA023_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .int_reset_mask = BMA023_INT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .sleep_reg = BMA023_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .sleep_mask = BMA023_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .bw_reg = BMA023_CTRL_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .bw_mask = BMA023_BW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .scale_reg = BMA023_CTRL_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .scale_mask = BMA023_RANGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* No power mode on bma023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .power_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .power_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .lowpower_val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .int_enable_reg = BMA023_CTRL_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .int_enable_mask = BMA023_NEW_DATA_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .softreset_reg = BMA023_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .softreset_val = BMA023_RESET_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .chip_config = bma023_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .chip_disable = bma023_chip_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [BMA150] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .chip_id = BMA023_ID_REG_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .channels = bma150_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .num_channels = ARRAY_SIZE(bma150_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .scale_table = bma023_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .num_scales = ARRAY_SIZE(bma023_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .bw_table = bma023_bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .num_bw = ARRAY_SIZE(bma023_bw_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .temp_offset = -60, /* 0 LSB @ -30 degree C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .int_reset_reg = BMA023_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .int_reset_mask = BMA023_INT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .sleep_reg = BMA023_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .sleep_mask = BMA023_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .bw_reg = BMA023_CTRL_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .bw_mask = BMA023_BW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .scale_reg = BMA023_CTRL_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .scale_mask = BMA023_RANGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* No power mode on bma150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .power_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .power_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .lowpower_val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .int_enable_reg = BMA023_CTRL_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .int_enable_mask = BMA023_NEW_DATA_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .softreset_reg = BMA023_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .softreset_val = BMA023_RESET_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .chip_config = bma023_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .chip_disable = bma023_chip_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [BMA180] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .chip_id = BMA180_ID_REG_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .channels = bma180_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .num_channels = ARRAY_SIZE(bma180_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .scale_table = bma180_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .num_scales = ARRAY_SIZE(bma180_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .bw_table = bma180_bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .num_bw = ARRAY_SIZE(bma180_bw_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .temp_offset = 48, /* 0 LSB @ 24 degree C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .int_reset_reg = BMA180_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .int_reset_mask = BMA180_RESET_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .sleep_reg = BMA180_CTRL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .sleep_mask = BMA180_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .bw_reg = BMA180_BW_TCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .bw_mask = BMA180_BW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .scale_reg = BMA180_OFFSET_LSB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .scale_mask = BMA180_RANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .power_reg = BMA180_TCO_Z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .power_mask = BMA180_MODE_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .lowpower_val = BMA180_LOW_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .int_enable_reg = BMA180_CTRL_REG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .int_enable_mask = BMA180_NEW_DATA_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .softreset_reg = BMA180_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .softreset_val = BMA180_RESET_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .chip_config = bma180_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .chip_disable = bma180_chip_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) [BMA250] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .chip_id = BMA250_ID_REG_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .channels = bma250_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .num_channels = ARRAY_SIZE(bma250_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .scale_table = bma25x_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .num_scales = ARRAY_SIZE(bma25x_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .bw_table = bma25x_bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .num_bw = ARRAY_SIZE(bma25x_bw_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .temp_offset = 48, /* 0 LSB @ 24 degree C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .int_reset_reg = BMA250_INT_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .int_reset_mask = BMA250_INT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .sleep_reg = BMA250_POWER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .sleep_mask = BMA250_SUSPEND_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .bw_reg = BMA250_BW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .bw_mask = BMA250_BW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .bw_offset = BMA250_BW_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .scale_reg = BMA250_RANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .scale_mask = BMA250_RANGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .power_reg = BMA250_POWER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .power_mask = BMA250_LOWPOWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .lowpower_val = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .int_enable_reg = BMA250_INT_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .int_enable_mask = BMA250_DATA_INTEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .int_map_reg = BMA250_INT_MAP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .int_enable_dataready_int1_mask = BMA250_INT1_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .softreset_reg = BMA250_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .softreset_val = BMA180_RESET_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .chip_config = bma25x_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .chip_disable = bma25x_chip_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [BMA254] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .chip_id = BMA254_ID_REG_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .channels = bma254_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .num_channels = ARRAY_SIZE(bma254_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .scale_table = bma25x_scale_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .num_scales = ARRAY_SIZE(bma25x_scale_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .bw_table = bma25x_bw_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .num_bw = ARRAY_SIZE(bma25x_bw_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .temp_offset = 46, /* 0 LSB @ 23 degree C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .int_reset_reg = BMA254_INT_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .int_reset_mask = BMA254_INT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .sleep_reg = BMA254_POWER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .sleep_mask = BMA254_SUSPEND_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .bw_reg = BMA254_BW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .bw_mask = BMA254_BW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .bw_offset = BMA254_BW_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .scale_reg = BMA254_RANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .scale_mask = BMA254_RANGE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .power_reg = BMA254_POWER_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .power_mask = BMA254_LOWPOWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .lowpower_val = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .int_enable_reg = BMA254_INT_ENABLE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .int_enable_mask = BMA254_DATA_INTEN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .int_map_reg = BMA254_INT_MAP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .int_enable_dataready_int1_mask = BMA254_INT1_DATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .softreset_reg = BMA254_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .softreset_val = BMA180_RESET_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .chip_config = bma25x_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .chip_disable = bma25x_chip_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static irqreturn_t bma180_trigger_handler(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct iio_poll_func *pf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct iio_dev *indio_dev = pf->indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) s64 time_ns = iio_get_time_ns(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int bit, ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) for_each_set_bit(bit, indio_dev->active_scan_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) indio_dev->masklength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = bma180_get_data_reg(data, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) data->scan.chan[i++] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, time_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) iio_trigger_notify_done(indio_dev->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int bma180_data_rdy_trigger_set_state(struct iio_trigger *trig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return bma180_set_new_data_intr_state(data, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int bma180_trig_try_reen(struct iio_trigger *trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return bma180_reset_intr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const struct iio_trigger_ops bma180_trigger_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .set_trigger_state = bma180_data_rdy_trigger_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .try_reenable = bma180_trig_try_reen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int bma180_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct bma180_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct iio_dev *indio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) enum chip_ids chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!indio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) i2c_set_clientdata(client, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) chip = (enum chip_ids)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) chip = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) data->part_info = &bma180_part_info[chip];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ret = iio_read_mount_matrix(dev, "mount-matrix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) &data->orientation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) data->vdd_supply = devm_regulator_get(dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (IS_ERR(data->vdd_supply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return dev_err_probe(dev, PTR_ERR(data->vdd_supply),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "Failed to get vdd regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) data->vddio_supply = devm_regulator_get(dev, "vddio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (IS_ERR(data->vddio_supply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return dev_err_probe(dev, PTR_ERR(data->vddio_supply),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "Failed to get vddio regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Typical voltage 2.4V these are min and max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = regulator_set_voltage(data->vdd_supply, 1620000, 3600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = regulator_set_voltage(data->vddio_supply, 1200000, 3600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = regulator_enable(data->vdd_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) dev_err(dev, "Failed to enable vdd regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = regulator_enable(data->vddio_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_err(dev, "Failed to enable vddio regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) goto err_disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Wait to make sure we started up properly (3 ms at least) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = data->part_info->chip_config(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) goto err_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mutex_init(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) indio_dev->channels = data->part_info->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) indio_dev->num_channels = data->part_info->num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) indio_dev->name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) indio_dev->modes = INDIO_DIRECT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) indio_dev->info = &bma180_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) data->trig = iio_trigger_alloc("%s-dev%d", indio_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) indio_dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!data->trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) goto err_chip_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = devm_request_irq(dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) iio_trigger_generic_data_rdy_poll, IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) "bma180_event", data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(dev, "unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) goto err_trigger_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) data->trig->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) data->trig->ops = &bma180_trigger_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) iio_trigger_set_drvdata(data->trig, indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) indio_dev->trig = iio_trigger_get(data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = iio_trigger_register(data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) goto err_trigger_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = iio_triggered_buffer_setup(indio_dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) bma180_trigger_handler, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(dev, "unable to setup iio triggered buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) goto err_trigger_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = iio_device_register(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(dev, "unable to register iio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto err_buffer_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) err_buffer_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) err_trigger_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (data->trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) iio_trigger_unregister(data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) err_trigger_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) iio_trigger_free(data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) err_chip_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) data->part_info->chip_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) regulator_disable(data->vddio_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) err_disable_vdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) regulator_disable(data->vdd_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int bma180_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct iio_dev *indio_dev = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) iio_device_unregister(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) iio_triggered_buffer_cleanup(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (data->trig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) iio_trigger_unregister(data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) iio_trigger_free(data->trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) data->part_info->chip_disable(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) regulator_disable(data->vddio_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) regulator_disable(data->vdd_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int bma180_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret = bma180_set_sleep_state(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static int bma180_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct bma180_data *data = iio_priv(indio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) mutex_lock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = bma180_set_sleep_state(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) mutex_unlock(&data->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define BMA180_PM_OPS (&bma180_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define BMA180_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const struct i2c_device_id bma180_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) { "bma023", BMA023 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) { "bma150", BMA150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) { "bma180", BMA180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) { "bma250", BMA250 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) { "bma254", BMA254 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) { "smb380", BMA150 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) MODULE_DEVICE_TABLE(i2c, bma180_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const struct of_device_id bma180_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .compatible = "bosch,bma023",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .data = (void *)BMA023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .compatible = "bosch,bma150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .data = (void *)BMA150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .compatible = "bosch,bma180",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .data = (void *)BMA180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .compatible = "bosch,bma250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .data = (void *)BMA250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .compatible = "bosch,bma254",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .data = (void *)BMA254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .compatible = "bosch,smb380",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .data = (void *)BMA150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) MODULE_DEVICE_TABLE(of, bma180_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static struct i2c_driver bma180_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .name = "bma180",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .pm = BMA180_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .of_match_table = bma180_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .probe = bma180_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .remove = bma180_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .id_table = bma180_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) module_i2c_driver(bma180_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) MODULE_AUTHOR("Kravchenko Oleksandr <x0199363@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) MODULE_AUTHOR("Texas Instruments, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) MODULE_DESCRIPTION("Bosch BMA023/BMA1x0/BMA25x triaxial acceleration sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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