^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * intel_idle.c - native hardware idle loop for modern Intel processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 - 2020, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Len Brown <len.brown@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * in lieu of the legacy ACPI processor_idle driver. The intent is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * make Linux more efficient on these processors, as intel_idle knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Design Assumptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * All CPUs have same idle states as boot CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Chipset BM_STS (bus master status) bit is a NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * for preventing entry into deep C-states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * CPU will flush caches as needed when entering a C-state via MWAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * (in contrast to entering ACPI C3, in which case the WBINVD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * instruction needs to be executed to flush the caches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Known limitations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * ACPI has a .suspend hack to turn off deep c-statees during suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * to avoid complications with the lapic timer workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Have not seen issues with suspend, but may need same workaround here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* un-comment DEBUG to enable pr_debug() statements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/tick.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <trace/events/power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/intel-family.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/mwait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define INTEL_IDLE_VERSION "0.5.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct cpuidle_driver intel_idle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "intel_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* intel_idle.max_cstate=0 disables driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int max_cstate = CPUIDLE_STATE_MAX - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static unsigned int disabled_states_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static unsigned long auto_demotion_disable_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static bool disable_promotion_to_c1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct idle_cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct cpuidle_state *state_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Hardware C-state auto-demotion may not always be optimal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Indicate which enable bits to clear here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long auto_demotion_disable_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool byt_auto_demotion_disable_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bool disable_promotion_to_c1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bool use_acpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct idle_cpu *icpu __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct cpuidle_state *cpuidle_state_table __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static unsigned int mwait_substates __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Enable this state by default even if the ACPI _CST does not list it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * MWAIT takes an 8-bit "hint" in EAX "suggesting"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * the C-state (top nibble) and sub-state (bottom nibble)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * We store the hint at the top of our "flags" for each state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * intel_idle - Ask the processor to enter the given idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @dev: cpuidle device of the target CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @drv: cpuidle driver (assumed to point to intel_idle_driver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @index: Target idle state index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Use the MWAIT instruction to notify the processor that the CPU represented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @dev is idle and it can try to enter the idle state corresponding to @index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * If the local APIC timer is not known to be reliable in the target idle state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * flushing user TLBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Must be called under local_irq_disable().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static __cpuidle int intel_idle(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct cpuidle_driver *drv, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct cpuidle_state *state = &drv->states[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long eax = flg2MWAIT(state->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long ecx = 1; /* break on interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mwait_idle_with_hints(eax, ecx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * intel_idle_s2idle - Ask the processor to enter the given idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @dev: cpuidle device of the target CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @drv: cpuidle driver (assumed to point to intel_idle_driver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @index: Target idle state index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Use the MWAIT instruction to notify the processor that the CPU represented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @dev is idle and it can try to enter the idle state corresponding to @index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * scheduler tick and suspended scheduler clock on the target CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct cpuidle_driver *drv, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long eax = flg2MWAIT(drv->states[index].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long ecx = 1; /* break on interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mwait_idle_with_hints(eax, ecx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * States are indexed by the cstate number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * which is also the index into the MWAIT hint array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Thus C0 is a dummy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct cpuidle_state nehalem_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .exit_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .target_residency = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .exit_latency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .target_residency = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .exit_latency = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .target_residency = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct cpuidle_state snb_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .exit_latency = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .target_residency = 211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .exit_latency = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .target_residency = 345,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .desc = "MWAIT 0x30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .exit_latency = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .target_residency = 345,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct cpuidle_state byt_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "C6N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .desc = "MWAIT 0x58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .exit_latency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .target_residency = 275,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .name = "C6S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .desc = "MWAIT 0x52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .exit_latency = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .target_residency = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .exit_latency = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .target_residency = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "C7S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .desc = "MWAIT 0x64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .exit_latency = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .target_residency = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct cpuidle_state cht_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "C6N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .desc = "MWAIT 0x58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .exit_latency = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .target_residency = 275,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "C6S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .desc = "MWAIT 0x52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .exit_latency = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .target_residency = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .name = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .exit_latency = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .target_residency = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "C7S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .desc = "MWAIT 0x64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .exit_latency = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .target_residency = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct cpuidle_state ivb_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .exit_latency = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .target_residency = 156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .exit_latency = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .target_residency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .desc = "MWAIT 0x30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .exit_latency = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .target_residency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct cpuidle_state ivt_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .target_residency = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .exit_latency = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .target_residency = 156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .exit_latency = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .target_residency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct cpuidle_state ivt_cstates_4s[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .target_residency = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .exit_latency = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .target_residency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .exit_latency = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .target_residency = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct cpuidle_state ivt_cstates_8s[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .target_residency = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .exit_latency = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .target_residency = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .exit_latency = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .target_residency = 700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct cpuidle_state hsw_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .exit_latency = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .target_residency = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .exit_latency = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .target_residency = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .name = "C7s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .desc = "MWAIT 0x32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .exit_latency = 166,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .target_residency = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .name = "C8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .desc = "MWAIT 0x40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .exit_latency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .target_residency = 900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "C9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .desc = "MWAIT 0x50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .exit_latency = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .target_residency = 1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "C10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .exit_latency = 2600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .target_residency = 7700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static struct cpuidle_state bdw_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .exit_latency = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .target_residency = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .exit_latency = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .target_residency = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "C7s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .desc = "MWAIT 0x32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .exit_latency = 166,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .target_residency = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .name = "C8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .desc = "MWAIT 0x40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .exit_latency = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .target_residency = 900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .name = "C9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .desc = "MWAIT 0x50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .exit_latency = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .target_residency = 1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .name = "C10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .exit_latency = 2600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .target_residency = 7700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct cpuidle_state skl_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "C3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .exit_latency = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .target_residency = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .exit_latency = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .target_residency = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .name = "C7s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .desc = "MWAIT 0x33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .exit_latency = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .target_residency = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .name = "C8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .desc = "MWAIT 0x40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .exit_latency = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .target_residency = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .name = "C9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .desc = "MWAIT 0x50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .exit_latency = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .target_residency = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .name = "C10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .exit_latency = 890,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .target_residency = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static struct cpuidle_state skx_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .exit_latency = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .target_residency = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static struct cpuidle_state icx_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .target_residency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .exit_latency = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .target_residency = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .exit_latency = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .target_residency = 384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static struct cpuidle_state atom_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .name = "C2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .flags = MWAIT2flg(0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .exit_latency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .target_residency = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = "C4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .desc = "MWAIT 0x30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .exit_latency = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .target_residency = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .desc = "MWAIT 0x52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .exit_latency = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .target_residency = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static struct cpuidle_state tangier_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .target_residency = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .name = "C4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .desc = "MWAIT 0x30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .exit_latency = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .target_residency = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .desc = "MWAIT 0x52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .exit_latency = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .target_residency = 560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .name = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .exit_latency = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .target_residency = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = "C9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .desc = "MWAIT 0x64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .exit_latency = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .target_residency = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct cpuidle_state avn_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .desc = "MWAIT 0x51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .exit_latency = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .target_residency = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static struct cpuidle_state knl_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .exit_latency = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .enter_s2idle = intel_idle_s2idle },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .desc = "MWAIT 0x10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .exit_latency = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .target_residency = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .enter_s2idle = intel_idle_s2idle },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static struct cpuidle_state bxt_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .exit_latency = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .target_residency = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "C7s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .desc = "MWAIT 0x31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .exit_latency = 155,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .target_residency = 155,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = "C8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .desc = "MWAIT 0x40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .exit_latency = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .target_residency = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .name = "C9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .desc = "MWAIT 0x50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .exit_latency = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .target_residency = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .name = "C10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .desc = "MWAIT 0x60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .exit_latency = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .target_residency = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static struct cpuidle_state dnv_cstates[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .name = "C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .desc = "MWAIT 0x00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .flags = MWAIT2flg(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .exit_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .target_residency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .name = "C1E",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .desc = "MWAIT 0x01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .exit_latency = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .target_residency = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .name = "C6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .desc = "MWAIT 0x20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .exit_latency = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .target_residency = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .enter = &intel_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .enter_s2idle = intel_idle_s2idle, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .enter = NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const struct idle_cpu idle_cpu_nehalem __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .state_table = nehalem_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const struct idle_cpu idle_cpu_nhx __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .state_table = nehalem_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const struct idle_cpu idle_cpu_atom __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .state_table = atom_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const struct idle_cpu idle_cpu_tangier __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .state_table = tangier_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const struct idle_cpu idle_cpu_lincroft __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .state_table = atom_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct idle_cpu idle_cpu_snb __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .state_table = snb_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const struct idle_cpu idle_cpu_snx __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .state_table = snb_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const struct idle_cpu idle_cpu_byt __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .state_table = byt_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .byt_auto_demotion_disable_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct idle_cpu idle_cpu_cht __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .state_table = cht_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .byt_auto_demotion_disable_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static const struct idle_cpu idle_cpu_ivb __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .state_table = ivb_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static const struct idle_cpu idle_cpu_ivt __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .state_table = ivt_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const struct idle_cpu idle_cpu_hsw __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .state_table = hsw_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct idle_cpu idle_cpu_hsx __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .state_table = hsw_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const struct idle_cpu idle_cpu_bdw __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .state_table = bdw_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static const struct idle_cpu idle_cpu_bdx __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .state_table = bdw_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct idle_cpu idle_cpu_skl __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .state_table = skl_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const struct idle_cpu idle_cpu_skx __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .state_table = skx_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const struct idle_cpu idle_cpu_icx __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .state_table = icx_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const struct idle_cpu idle_cpu_avn __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .state_table = avn_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const struct idle_cpu idle_cpu_knl __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .state_table = knl_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const struct idle_cpu idle_cpu_bxt __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .state_table = bxt_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const struct idle_cpu idle_cpu_dnv __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .state_table = dnv_cstates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .disable_promotion_to_c1e = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .use_acpi = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static const struct x86_cpu_id intel_idle_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_dnv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static bool __init intel_idle_max_cstate_reached(int cstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (cstate + 1 > max_cstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pr_info("max_cstate %d reached\n", max_cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) unsigned long eax = flg2MWAIT(state->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (boot_cpu_has(X86_FEATURE_ARAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * Switch over to one-shot tick broadcast if the target C-state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * is deeper than C1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #include <acpi/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static bool no_acpi __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) module_param(no_acpi, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) module_param_named(use_acpi, force_use_acpi, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static struct acpi_processor_power acpi_state_table __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * intel_idle_cst_usable - Check if the _CST information can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * Check if all of the C-states listed by _CST in the max_cstate range are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static bool __init intel_idle_cst_usable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int cstate, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) acpi_state_table.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) for (cstate = 1; cstate < limit; cstate++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (cx->entry_method != ACPI_CSTATE_FFH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static bool __init intel_idle_acpi_cst_extract(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (no_acpi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pr_debug("Not allowed to use ACPI _CST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct acpi_processor *pr = per_cpu(processors, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!pr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) acpi_state_table.count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (!intel_idle_cst_usable())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!acpi_processor_claim_cst_control())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) acpi_state_table.count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pr_debug("ACPI _CST not found or not usable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * the interesting states are ACPI_CSTATE_FFH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) for (cstate = 1; cstate < limit; cstate++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct acpi_processor_cx *cx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct cpuidle_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (intel_idle_max_cstate_reached(cstate - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) cx = &acpi_state_table.states[cstate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) state = &drv->states[drv->state_count++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) state->exit_latency = cx->latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * For C1-type C-states use the same number for both the exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * latency and target residency, because that is the case for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * C1 in the majority of the static C-states tables above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * For the other types of C-states, however, set the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * residency to 3 times the exit latency which should lead to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * a reasonable balance between energy-efficiency and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * performance in the majority of interesting cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) state->target_residency = cx->latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (cx->type > ACPI_STATE_C1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) state->target_residency *= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) state->flags = MWAIT2flg(cx->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (cx->type > ACPI_STATE_C2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (disabled_states_mask & BIT(cstate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) state->flags |= CPUIDLE_FLAG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (intel_idle_state_needs_timer_stop(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) state->flags |= CPUIDLE_FLAG_TIMER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) state->enter = intel_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) state->enter_s2idle = intel_idle_s2idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static bool __init intel_idle_off_by_default(u32 mwait_hint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) int cstate, limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * If there are no _CST C-states, do not disable any C-states by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (!acpi_state_table.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * the interesting states are ACPI_CSTATE_FFH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) for (cstate = 1; cstate < limit; cstate++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (acpi_state_table.states[cstate].address == mwait_hint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define force_use_acpi (false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static inline bool intel_idle_acpi_cst_extract(void) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * Tune IVT multi-socket targets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * Assumption: num_sockets == (max_package_num + 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void __init ivt_idle_state_table_update(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) int cpu, package_num, num_sockets = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) package_num = topology_physical_package_id(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (package_num + 1 > num_sockets) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) num_sockets = package_num + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (num_sockets > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) cpuidle_state_table = ivt_cstates_8s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (num_sockets > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) cpuidle_state_table = ivt_cstates_4s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* else, 1 and 2 socket systems use default ivt_cstates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * irtl_2_usec - IRTL to microseconds conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * @irtl: IRTL MSR value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static unsigned long long __init irtl_2_usec(unsigned long long irtl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const unsigned int irtl_ns_units[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) unsigned long long ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (!irtl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ns = irtl_ns_units[(irtl >> 10) & 0x7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * bxt_idle_state_table_update - Fix up the Broxton idle states table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * definitive maximum latency and use the same value for target_residency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static void __init bxt_idle_state_table_update(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) unsigned long long msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) unsigned int usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) rdmsrl(MSR_PKGC6_IRTL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) usec = irtl_2_usec(msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (usec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) bxt_cstates[2].exit_latency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) bxt_cstates[2].target_residency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) rdmsrl(MSR_PKGC7_IRTL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) usec = irtl_2_usec(msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (usec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) bxt_cstates[3].exit_latency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) bxt_cstates[3].target_residency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) rdmsrl(MSR_PKGC8_IRTL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) usec = irtl_2_usec(msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (usec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) bxt_cstates[4].exit_latency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) bxt_cstates[4].target_residency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) rdmsrl(MSR_PKGC9_IRTL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) usec = irtl_2_usec(msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (usec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) bxt_cstates[5].exit_latency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) bxt_cstates[5].target_residency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) rdmsrl(MSR_PKGC10_IRTL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) usec = irtl_2_usec(msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (usec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) bxt_cstates[6].exit_latency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) bxt_cstates[6].target_residency = usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static void __init sklh_idle_state_table_update(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) unsigned long long msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) unsigned int eax, ebx, ecx, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (max_cstate <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* if PC10 not present in CPUID.MWAIT.EDX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if ((mwait_substates & (0xF << 28)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* PC10 is not enabled in PKG C-state limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if ((msr & 0xF) != 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ecx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) cpuid(7, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* if SGX is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (ebx & (1 << 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) rdmsrl(MSR_IA32_FEAT_CTL, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* if SGX is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (msr & (1 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) MWAIT_SUBSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Ignore the C-state if there are NO sub-states in CPUID for it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (num_substates == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mark_tsc_unstable("TSC halts in idle states deeper than C2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) int cstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) switch (boot_cpu_data.x86_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case INTEL_FAM6_IVYBRIDGE_X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ivt_idle_state_table_update();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) case INTEL_FAM6_ATOM_GOLDMONT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) bxt_idle_state_table_update();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) case INTEL_FAM6_SKYLAKE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) sklh_idle_state_table_update();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) unsigned int mwait_hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (intel_idle_max_cstate_reached(cstate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!cpuidle_state_table[cstate].enter &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) !cpuidle_state_table[cstate].enter_s2idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* If marked as unusable, skip this state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) pr_debug("state %s is disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) cpuidle_state_table[cstate].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (!intel_idle_verify_cstate(mwait_hint))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Structure copy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) drv->states[drv->state_count] = cpuidle_state_table[cstate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if ((disabled_states_mask & BIT(drv->state_count)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ((icpu->use_acpi || force_use_acpi) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) intel_idle_off_by_default(mwait_hint) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (intel_idle_state_needs_timer_stop(&drv->states[drv->state_count]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) drv->states[drv->state_count].flags |= CPUIDLE_FLAG_TIMER_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) drv->state_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (icpu->byt_auto_demotion_disable_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * intel_idle_cpuidle_driver_init - Create the list of available idle states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * @drv: cpuidle driver structure to initialize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) cpuidle_poll_state_init(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (disabled_states_mask & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) drv->states[0].flags |= CPUIDLE_FLAG_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) drv->state_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (icpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) intel_idle_init_cstates_icpu(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) intel_idle_init_cstates_acpi(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static void auto_demotion_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) unsigned long long msr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) msr_bits &= ~auto_demotion_disable_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static void c1e_promotion_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) unsigned long long msr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) msr_bits &= ~0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * @cpu: CPU to initialize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * Register a cpuidle device object for @cpu and update its MSRs in accordance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * with the processor model flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static int intel_idle_cpu_init(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct cpuidle_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) dev->cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (cpuidle_register_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) pr_debug("cpuidle_register_device %d failed!\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (auto_demotion_disable_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) auto_demotion_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (disable_promotion_to_c1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) c1e_promotion_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static int intel_idle_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct cpuidle_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (!boot_cpu_has(X86_FEATURE_ARAT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) tick_broadcast_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * Some systems can hotplug a cpu at runtime after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * the kernel has booted, we have to initialize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * driver in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (!dev->registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return intel_idle_cpu_init(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static void __init intel_idle_cpuidle_devices_uninit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) for_each_online_cpu(i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static int __init intel_idle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) const struct x86_cpu_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) unsigned int eax, ebx, ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* Do not load intel_idle at all for now if idle= is passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (boot_option_idle_override != IDLE_NO_OVERRIDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (max_cstate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pr_debug("disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) id = x86_match_cpu(intel_idle_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pr_debug("Please enable MWAIT in BIOS SETUP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) id = x86_match_cpu(intel_mwait_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) !mwait_substates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) icpu = (const struct idle_cpu *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (icpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) cpuidle_state_table = icpu->state_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (icpu->use_acpi || force_use_acpi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) intel_idle_acpi_cst_extract();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) } else if (!intel_idle_acpi_cst_extract()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) boot_cpu_data.x86_model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!intel_idle_cpuidle_devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) intel_idle_cpuidle_driver_init(&intel_idle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) retval = cpuidle_register_driver(&intel_idle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct cpuidle_driver *drv = cpuidle_get_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) drv ? drv->name : "none");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) goto init_driver_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) intel_idle_cpu_online, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) goto hp_setup_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) pr_debug("Local APIC timer is reliable in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) hp_setup_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) intel_idle_cpuidle_devices_uninit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) cpuidle_unregister_driver(&intel_idle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) init_driver_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) free_percpu(intel_idle_cpuidle_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) device_initcall(intel_idle_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * We are not really modular, but we used to support that. Meaning we also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * support "intel_idle.max_cstate=..." at boot and also a read-only export of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * is the easiest way (currently) to continue doing that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) module_param(max_cstate, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * The positions of the bits that are set in this number are the indices of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * idle states to be disabled by default (as reflected by the names of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * corresponding idle state directories in sysfs, "state0", "state1" ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * "state<i>" ..., where <i> is the index of the given state).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) module_param_named(states_off, disabled_states_mask, uint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) MODULE_PARM_DESC(states_off, "Mask of disabled idle states");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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