^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * VIA IDE driver for Linux. Supported southbridges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * vt8235, vt8237, vt8237a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2000-2002 Vojtech Pavlik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on the work of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Michel Aubry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Jeff Garzik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Andre Hedrick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Obsolete device documentation publicly available from via.com.tw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Current device documentation available under NDA only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_PPC_CHRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRV_NAME "via82cxxx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIA_IDE_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIA_IDE_CONFIG 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VIA_FIFO_CONFIG 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VIA_MISC_1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIA_MISC_2 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VIA_MISC_3 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VIA_DRIVE_TIMING 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIA_8BIT_TIMING 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VIA_ADDRESS_SETUP 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VIA_UDMA_TIMING 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * VIA SouthBridge chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct via_isa_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 rev_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 rev_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 udma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } via_isa_bridges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static unsigned int via_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct via82cxxx_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct via_isa_bridge *via_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int via_80w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * via_set_speed - write timing registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @dn: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @timing: IDE timing data to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * via_set_speed writes timing values to the chipset registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct via82cxxx_dev *vdev = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (~vdev->via_config->flags & VIA_BAD_AST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) switch (vdev->via_config->udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Set UDMA unless device is not UDMA capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (vdev->via_config->udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 udma_etc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* clear transfer mode bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) udma_etc &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (timing->udma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* preserve 80-wire cable detection bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) udma_etc &= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) udma_etc |= t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * via_set_drive - configure transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @drive: Drive to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * via_set_drive() computes timing values configures the chipset to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * a desired transfer mode. It also can be called by upper layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ide_drive_t *peer = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ide_host *host = dev_get_drvdata(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct via82cxxx_dev *vdev = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct ide_timing t, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int T, UT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) T = 1000000000 / via_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) switch (vdev->via_config->udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case ATA_UDMA2: UT = T; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case ATA_UDMA4: UT = T/2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case ATA_UDMA5: UT = T/3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case ATA_UDMA6: UT = T/4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) default: UT = T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ide_timing_compute(drive, speed, &t, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (peer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) via_set_speed(hwif, drive->dn, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * via_set_pio_mode - set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * A callback from the upper layers for PIO-only tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) drive->dma_mode = drive->pio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) via_set_drive(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct via_isa_bridge *via_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (via_config = via_isa_bridges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) !!(via_config->flags & VIA_BAD_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) via_config->id, NULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if ((*isa)->revision >= via_config->rev_min &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (*isa)->revision <= via_config->rev_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pci_dev_put(*isa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return via_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Check and handle 80-wire cable presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (vdev->via_config->udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case ATA_UDMA4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 24; i >= 0; i -= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (((u >> (i & 16)) & 8) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ((u >> i) & 0x20) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (((u >> i) & 7) < 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * 2x PCI clock and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * UDMA w/ < 3T/cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) vdev->via_80w |= (1 << (1 - (i >> 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case ATA_UDMA5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 24; i >= 0; i -= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (((u >> i) & 0x10) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (((u >> i) & 0x20) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (((u >> i) & 7) < 4))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* BIOS 80-wire bit or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * UDMA w/ < 60ns/cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) vdev->via_80w |= (1 << (1 - (i >> 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case ATA_UDMA6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (i = 24; i >= 0; i -= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (((u >> i) & 0x10) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (((u >> i) & 0x20) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (((u >> i) & 7) < 6))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* BIOS 80-wire bit or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * UDMA w/ < 60ns/cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) vdev->via_80w |= (1 << (1 - (i >> 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * init_chipset_via82cxxx - initialization handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * The initialization callback. Here we determine the IDE chip type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * and initialize its drive independent registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int init_chipset_via82cxxx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct via82cxxx_dev *vdev = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct via_isa_bridge *via_config = vdev->via_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u8 t, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Detect cable and configure Clk66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) via_cable_detect(vdev, u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (via_config->udma_mask == ATA_UDMA4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Enable Clk66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else if (via_config->flags & VIA_BAD_CLK66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Would cause trouble on 596a and 686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Check whether interfaces are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Set up FIFO sizes and thresholds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Disable PREQ# till DDACK# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (via_config->flags & VIA_BAD_PREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Would crash on 586b rev 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) t &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Fix FIFO split between channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (via_config->flags & VIA_SET_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) t &= (t & 0x9f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch (v & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 2: t |= 0x00; break; /* 16 on primary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case 1: t |= 0x60; break; /* 16 on secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case 3: t |= 0x20; break; /* 8 pri 8 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Cable special cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct dmi_system_id cable_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .ident = "Acer Ferrari 3400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int via_cable_override(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Systems by DMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (dmi_check_system(cable_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Arima W730-K8/Targa Visionary 811/... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pdev->subsystem_vendor == 0x161F &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pdev->subsystem_device == 0x2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ide_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct via82cxxx_dev *vdev = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (via_cable_override(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ATA_CBL_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if ((vdev->via_80w >> hwif->channel) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct ide_port_ops via_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .set_pio_mode = via_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .set_dma_mode = via_set_drive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .cable_detect = via82cxxx_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct ide_port_info via82cxxx_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .init_chipset = init_chipset_via82cxxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .port_ops = &via_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) IDE_HFLAG_POST_SET_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) IDE_HFLAG_IO_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .pio_mask = ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .swdma_mask = ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct pci_dev *isa = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct via_isa_bridge *via_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct via82cxxx_dev *vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) d = via82cxxx_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Find the ISA bridge and check we know what it is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) via_config = via_config_find(&isa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Print the boot message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pci_name(dev), via_config->name, isa->revision,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) via_config->udma_mask ? "U" : "MW",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) via_dma[via_config->udma_mask ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (fls(via_config->udma_mask) - 1) : 0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pci_dev_put(isa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Determine system bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) switch (via_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 33000: via_clock = 33333; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case 37000: via_clock = 37500; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case 41000: via_clock = 41666; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (via_clock < 20000 || via_clock > 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "impossible (%d), using 33 MHz instead.\n", via_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) via_clock = 33333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (idx == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) d.enablebits[1].reg = d.enablebits[0].reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) d.host_flags |= IDE_HFLAG_NO_AUTODMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (idx == VIA_IDFLAG_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) d.host_flags |= IDE_HFLAG_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if ((via_config->flags & VIA_NO_UNMASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) d.udma_mask = via_config->udma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!vdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) vdev->via_config = via_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rc = ide_pci_init_one(dev, &d, vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) kfree(vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void via_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct via82cxxx_dev *vdev = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) kfree(vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct pci_device_id via_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_DEVICE_TABLE(pci, via_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct pci_driver via_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "VIA_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .id_table = via_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .probe = via_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .remove = via_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int __init via_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ide_pci_register_driver(&via_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void __exit via_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pci_unregister_driver(&via_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) module_init(via_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) module_exit(via_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_DESCRIPTION("PCI driver module for VIA IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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